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參數(shù)資料
| 型號： | AD9547BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9547 Mask Change 20/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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AD9547
Data Sheet
Rev. E | Page 38 of 104
2×
÷N
VCO
CALIBRATION
LOCK
DETECT
SYSTEM
CLOCK
÷M
LOOP
FILTER
SYSCLKN
SYSCLKP
SYSCLK_VREG
SYSCLK_LF
HF
XTAL
LF
34
37
38
35
PFD
AND
CHARGE
PUMP
08300-
020
Figure 44. System Clock Block Diagram
The LF path permits the user to provide an LVPECL, LVDS,
CMOS, or sinusoidal low frequency clock for multiplication
by the integrated SYSCLK PLL. The LF path handles input
frequencies from 3.5 MHz up to 100 MHz. However, when
using a sinusoidal input signal, it is best to use a frequency in
excess of 20 MHz. Otherwise, the resulting low slew rate can
lead to substandard noise performance. Note that the LF path
includes an optional 2× frequency multiplier to double the rate
at the input to the SYSCLK PLL and potentially reduce the PLL
in-band noise. However, to avoid exceeding the maximum PFD
rate of 150 MHz, use of the 2× frequency multiplier is valid only
for input frequencies below 125 MHz.
The XTAL path enables the connection of a crystal resonator
(typically 10 MHz to 50 MHz) across the SYSCLKx input pins.
An internal amplifier provides the negative resistance required
to induce oscillation. The internal amplifier expects a 3.2 mm ×
2.5 mm AT cut, fundamental mode crystal with a maximum
motional resistance of 100 Ω. The following crystals, listed in
alphabetical order, may meet these criteria. Note that, although
these crystals meet the preceding criteria according to their data
sheets, Analog Devices, Inc., does not guarantee their operation
with the AD9547, nor does Analog Devices endorse one crystal
manufacturer/supplier over another.
AVX/Kyocera CX3225SB
ECS ECX-32
Epson/Toyocom TSX-3225
NDK NX3225SA
Siward SX-3225
SYSCLK PLL MULTIPLIER
The SYSCLK PLL multiplier is an integer-N design and relies on
an integrated LC tank and VCO. It provides a means to convert
a low frequency clock input to the desired system clock frequency,
fS (900 MHz to 1 GHz). The SYSCLK PLL multiplier accepts input
signals between 3.5 MHz and 500 MHz, but frequencies in excess
of 150 MHz require the M-divider to ensure compliance with
the maximum PFD rate (150 MHz). The PLL contains a feedback
divider (N) that is programmable for divide values between 6 and
255. The nominal VCO gain is 70 MHz/V.
Lock Detector
The SYSCLK PLL has a built-in lock detector. Register 0x0100,
Bit 2 determines whether the lock detector is active. When it
is active (default), the user controls the sensitivity of the lock
detector via the lock detect divider bits (Register 0x0100, Bits[1:0]).
Note that a value of zero must be written to the system clock
stability timer (Register 0x0106 to Register 0x0108) whenever
the lock detector is disabled (Register 0x0100, Bit 2 = 1).
The SYSCLK PLL phase detector operates at the PFD rate, which is
fVCO/N. Each PFD sample indicates whether the reference and feed-
back signals are phase aligned (within a certain threshold range).
While the PLL is in the process of acquiring a lock condition,
the PFD samples typically consist of an arbitrary sequence of
in-phase and out-of-phase indications. As the PLL approaches
complete phase lock, the number of consecutive in-phase PFD
samples grows larger. Thus, one way of indicating a locked
condition is to count the number of consecutive in-phase PFD
samples and, if it exceeds a certain value, declare the PLL locked.
This is exactly the role of the lock detect divider bits. When the
lock detector is enabled (Register 0x0100, Bit 2 = 0), the lock detect
divider bits determine the number of consecutive in-phase
decisions that are required (128, 256, 512, or 1024) before the lock
detector declares a locked condition. The default setting is 128.
Charge Pump
The charge pump operates in either automatic or manual mode,
based on the charge pump mode bit (Register 0x0100, Bit 6).
When Register 0x0100, Bit 6 = 0, the AD9547 automatically selects
the appropriate charge pump current based on the N divider value.
Note that the user does not have control of the charge pump cur-
rent bits (Register 0x0100, Bits[5:3]) in automatic mode. When
Register 0x0100, Bit 6 = 1, the user determines the charge pump
current via the charge pump current bits (Register 0x0100,
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| AD9547BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9548 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad/Octal Input Network Clock Generator/Synchronizer |
| AD9548/PCBZ | 功能描述:BOARD EVAL FOR AD9548 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9548/PCBZ | 制造商:Analog Devices 功能描述:Clock Generator Evaluation Board |
| AD9548BCPZ | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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