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參數(shù)資料
| 型號： | AD9547BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9547 Mask Change 20/Oct/2010 |
| 標(biāo)準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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Data Sheet
AD9547
Rev. E | Page 27 of 104
REFERENCE CLOCK INPUTS
Two pairs of pins provide access to the reference clock receivers.
Each pair is configurable either as a single differential receiver
or as two independent single-ended receivers. To accommodate
input signals with slowrising and falling edges, both the differential
and single-ended input receivers employ hysteresis. Hysteresis also
ensures that a disconnected or floating input does not cause the
receiver to oscillate spontaneously.
When configured for differential operation, the input receivers
accommodate either ac- or dc-coupled input signals. The receiver
is internally dc biased to handle ac-coupled operation.
When configured for single-ended operation, the input receivers
exhibit a pull-down load of 45 k (typical). Three user program-
mable threshold voltage ranges are available for each single-ended
receiver.
REFERENCE MONITORS
The reference monitors depend on a known and accurate system
clock period. Therefore, the functioning of the reference monitors
is not reliable untilthe system clock is stable. To avoid an incorrect
valid indication, the reference monitors indicate fault status until
the system clock stability timer expires (see the System Clock
Period section).
ReferencePeriodMonitor
Each reference input has a dedicated monitor that repeatedly
measures the reference period. The AD9547 uses the reference
period measurements to determine the validity of the reference
based on a set of user provided parameters in the profile register
area of the register map (see the Profile Registers (Register
0x0600 to Register 0x07FF) section). The AD9547 also uses the
reference period monitor to assign a particular reference to a
profile when the user programs the device for automatic profile
assignment.
The monitor works by comparing the measured period of a parti-
cular reference input against the parameters stored in the profile
register assigned to that same reference input. The parameters
include the reference period, an inner tolerance, and an outer
tolerance. A 40-bit number defines the reference period in units
of femtoseconds (fs). The 40-bit range allows for a reference period
entry of up to 1.1 ms (909 Hz). A 20-bit number defines the inner
and outer tolerances. The value stored in the register is the
reciprocal of the tolerance specification. For example, a tolerance
specification of 50 ppm yields a register value of 1/(50 ppm) =
1/0.000050 = 20,000 (0x04E20).
The use of two tolerance values provides hysteresis for the monitor
decision logic. The inner tolerance applies to a previously faulted
reference and specifies the largest period tolerance that a previously
faulted reference can exhibit before it qualifies as nonfaulted.
The outer tolerance applies toan already nonfaulted reference and
specifies the largest period tolerance that a nonfaulted reference
can exhibit before being faulted.
To produce decision hysteresis, the inner tolerance must be less
than the outer tolerance. That is, a faulted reference must meet
tighter requirements to become nonfaulted than a nonfaulted
reference must meet to become faulted.
ReferenceValidationTimer
Each reference input has a dedicated validation timer. The
validation timer establishes the amount of time that a previously
faulted reference must remain fault free before the AD9547
declares it to be nonfaulted. The timeout period of the validation
timer is programmable via a 16-bit register (see the validation
register contained within each of the eight profile registers in
the register map, Address 0x0600 to Address 0x07FF). The
16-bit number stored in the validation register represents units
of milliseconds, which yields a maximum timeout period of
65,535 ms.
Note that a validation period of zero must be programmed to
disable the validation timer. With the validation timer disabled,
the user must validate a reference manually via the force vali-
dation timeout register (Address 0x0A0E).
ReferenceRedetect Timer
Each reference input has a dedicated redetect timer. The redetect
timer is useful only when the device is programmed for automatic
profile selection. The redetect timer establishes the amount of
time that a reference must remain faulted before the AD9547
attempts to reassign it to a new profile. The timeout period of
the redetect timer is programmable via a 16-bit register (see the
redetect timer register contained within each of the eight profile
registers in the register map, Address 0x0600 toAddress 0x07FF).
The 16-bit number stored in the redetect timer register represents
units of milliseconds, which yields a maximum timeout period
of 65,535 ms.
Note that a timeout period of 0 must be programmed to disable the
redetect timer.
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| AD9547BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9548 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad/Octal Input Network Clock Generator/Synchronizer |
| AD9548/PCBZ | 功能描述:BOARD EVAL FOR AD9548 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9548/PCBZ | 制造商:Analog Devices 功能描述:Clock Generator Evaluation Board |
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