參數(shù)資料
型號(hào)： AD9547BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 99/104頁
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9547 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
AD9547
Data Sheet
Rev. E | Page 94 of 104
Table 139. IRQ Monitor for History Update, FrequencyLimit, and Phase Slew Limit
Address
Bit
Bit Name
Description
0x0D05
[7:5]
Unused
Unused.
4
History updated
Indicates the occurrence of a tuning word history update.
3
Frequency unclamped
Indicates a frequency limiter state transitionfrom clampedto unclamped.
2
Frequency clamped
Indicates a frequency limiter state transitionfrom unclamped to clamped.
1
Phase slew unlimited
Indicates a phase slew limiter state transitionfrom slew limitingto not slew limiting.
0
Phase slew limited
Indicates a phase slew limiter state transitionfrom not slew limitingto slew limiting.
Table 140. IRQ Monitor for ReferenceInputs
Address
Bit
Bit Name
Description
0x0D06
7
Ref AA new profile
Indicates that Ref AA has switched to a new profile.
6
Ref AA validated
Indicates that Ref AA has beenvalidated.
5
Ref AA fault cleared
Indicates that Ref AA has beenclearedof a previous fault.
4
Ref AA fault
Indicates that Ref AA has beenfaulted.
3
Ref A new profile
Indicates that Ref A has switched to a new profile.
2
Ref A validated
Indicates that Ref A has beenvalidated.
1
Ref A fault cleared
Indicates that Ref A has beenclearedof a previous fault.
0
Ref A fault
Indicates that Ref A has beenfaulted.
0x0D07
7
Ref BB new profile
Indicates that Ref BB has switched to a new profile.
6
Ref BB validated
Indicates that Ref BB has beenvalidated.
5
Ref BB fault cleared
Indicates that Ref BB has beenclearedof a previous fault.
4
Ref BB fault
Indicates that Ref BB has beenfaulted.
3
Ref B new profile
Indicates that Ref B has switched to a new profile.
2
Ref B validated
Indicates that Ref B has beenvalidated.
1
Ref B fault cleared
Indicates that Ref B has beenclearedof a previous fault.
0
Ref B fault
Indicates that Ref B has beenfaulted.
0x0D08
[7:0]
Unused
Unused.
0x0D09
[7:0]
Table 141. DPLL Status
Address
Bit
Bit Name
Description
0x0D0A
7
Offset slew limiting
The current closed-loop phase offset is rate limited.
6
Phase build-out
A phase build-out transition was made to the currently active reference.
5
Frequency lock
The DPLL has achieved frequency lock.
4
Phase lock
The DPLL has achieved phase lock.
3
Loop switching
The DPLL is in the process of a reference switchover.
2
Holdover
The DPLL is in holdover mode.
1
Active
The DPLL is active (that is, operating in a closed-loop condition).
0
Free running
The DPLL is free running (that is, operating in an open-loop condition).
0x0D0B
7
Frequency clamped
The upper or lower frequency tuning word clamp is in effect.
6
History available
There is sufficient tuning word history available for holdover operation.
[5:3]
Active reference priority
Priority value of the currently active reference.
000 = highest priority.
111 = lowest priority.
2
Unused
Unused.
[1:0]
Active reference
Index of the currently active reference.
00 = Reference A.
01 = Reference AA.
10 = Reference B.
11 = Reference BB.
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