參數(shù)資料
型號(hào): AD9547BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 97/104頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告: AD9547 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘/頻率發(fā)生器,同步器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 750kHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤(pán)
AD9547
Data Sheet
Rev. E | Page 92 of 104
Register0x0A0E to Register0x0A10—ReferenceValidationOverrideControls
Table 130. Force Validation Timeout1
Address
Bit
Bit Name
Description
0x0A0E
[7:4]
Unused
Unused.
3
Force Timeout BB
Setting this bit emulates timeout of the validation timer for Reference BB.
This is an autoclearing bit.
2
Force Timeout B
Setting this bit emulates timeout of the validation timer for Reference B.
This is an autoclearing bit.
1
Force Timeout AA
Setting this bit emulates timeout of the validation timer for Reference AA.
This is an autoclearing bit.
0
Force Timeout A
Setting this bit emulates timeout of the validation timer for Reference A.
This is an autoclearing bit.
1
All bits in this register are autoclearing.
Table 131. Reference Monitor Override1
Address
Bit
Bit Name
Description
0x0A0F
[7:4]
Unused
Unused.
3
Ref Mon Override BB
Overrides the reference monitorREFfault signal for ReferenceBB (default = 0, not overridden).
2
Ref Mon Override B
Overrides the referencemonitor REFfault signal for Reference B (default = 0, not overridden).
1
Ref Mon Override AA
Overrides the reference monitorREFfault signal for ReferenceAA (default = 0, not overridden).
0
Ref Mon Override A
Overrides the referencemonitor REFfault signal for Reference A (default = 0, not overridden).
1
All bits in this register are autoclearing.
Table 132. Reference Monitor Bypass1
Address
Bit
Bit Name
Description
0x0A10
[7:4]
Unused
Unused.
3
Ref Mon Bypass BB
Bypasses the reference monitor for Reference BB (default = 0, not bypassed).
2
Ref Mon Bypass B
Bypasses the reference monitor for Reference B (default = 0, not bypassed).
1
Ref Mon Bypass AA
Bypasses the reference monitor for Reference AA (default = 0, not bypassed).
0
Ref Mon Bypass A
Bypasses the reference monitor for Reference A (default = 0, not bypassed).
1
All bits in this register are autoclearing.
CLOCK PART SERIAL ID (REGISTER 0x0C00 TO REGISTER 0x0C07)
User programmable EEPROM ID registers.
Table 133. User Defined Identification Registers
Address
Bits
Bit Name
Description
0x0C00
[7:0]
User scratch pad[7:0]
User programmable EEPROM ID registers. These registers enable users to write a unique
code of their choosing to keep track of revisions to the EEPROM register loading. It has no
effect on part operation.The default EEPROM storage sequence must be alteredto include
0 = default.
0x0C01
[7:0]
User scratch pad[15:8]
0x0C02
[7:0]
User scratchpad[23:16]
0x0C03
[7:0]
User scratch pad[31:24]
0x0C04
[7:0]
User scratch pad[39:32]
0x0C05
[7:0]
User scratch pad[47:40]
0x0C06
[7:0]
User scratch pad[55:48]
0x0C07
[7:0]
User scratch pad[63:56]
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