參數(shù)資料
型號： AD9547BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 32/104頁
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9547 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
Data Sheet
AD9547
Rev. E | Page 33 of 104
programming the fixed phase lock offset bits (Address 0x030F to
Address 0x0313). The 40-bit word is a signed (twos complement)
number that represents units of picoseconds (ps).
In addition, the user can adjust the closed-loop phase offset (posi-
tive or negative) in incremental fashion. To do so, program the
desired step size in the incremental phase lock offset step size
bits (Address 0x0314 and Address 0x0315). This is an unsigned
number that represents units of picoseconds (ps). The program-
med step size is added to the current closed-loop phase offset each
time the user writes a Logic 1 to the increment phase offset bit
(Register 0x0A0C, Bit 0). Conversely, the programmed step size
is subtracted from the current closed-loop phase offset each time
the user writes a Logic 1 to the decrement phase offset bit
(Register 0x0A0C, Bit 1). The serial I/O port control logic clears
both of these bits automatically. The user can remove the incre-
mentally accumulated phase by writing a Logic 1 to the reset
incremental phase offset bit (Register 0x0A0C, Bit 2), which is
also cleared automatically. Alternatively, rather than using the
serial I/O port, the multifunction pins can be set up to perform
the increment, decrement, and clear functions.
Note that the incremental phase offset is completely independent of
the offset programmed into the fixed phase lock offset register.
However, if the phase slew limiter is active (see the Hitless
taneous change in closed-loop phase offset (fixed or incremental)
is subject to possible slew limitation by the action of the phase
slew limiter.
Programmable Digital Loop Filter
The AD9547 loop filter is a third-order digital IIR filter that is
analogous to the third-order analog loop shown in Figure 38.
C3
C2
C1
R2
R3
08
300-
0
15
Figure 38. Third-Order Analog Loop Filter
The filter requires four coefficients, as shown in Figure 39. The
AD9547 evaluation board software automatically generates the
required loop filter coefficient values based on user design criteria.
the design equations for calculating the loop filter coefficients
manually.
Each coefficient has a fractional component representing a value
from 0 up to, but not including, unity. Each also has an expo-
nential component representing a power of 2 with a negative
exponent. That is, the user enters a positive number (x) that the
hardware interprets as a negative exponent of two (2x). Thus,
the , and coefficients always represent values less than unity.
The coefficient, however, has two additional exponential
components, but the hardware interprets these as a positive
exponent of two (that is, 2x). This allows the coefficient to take
on values that are greater than unity. To provide sufficient dynamic
range, the positive exponent appears as two separate terms.
LOOP FILTER
(THIRD-ORDER IIR)
IN
OUT
FRACTIONAL
(16-BIT)
1/2x
(6-BIT)
α0
α
β0
β1
0
1
β
σ0
σ1
σ
α1
α2
α3
2x
(3-BIT)
2x
(4-BIT)
FRACTIONAL
(17-BIT)
1/2x
(6-BIT)
FRACTIONAL
(17-BIT)
1/2x
(6-BIT)
FRACTIONAL
(15-BIT)
1/2x
(5-BIT)
48
51
08300-
016
Figure 39. Third-Order Digital IIR Loop Filter
DPLL Phase Lock Detector
The DPLL contains an all-digital phase lock detector. The user
controls the threshold sensitivity and hysteresis of the phase
lock detector via the profile registers.
The phase lock detector behaves in a manner that is analogous
to water in a tub (see Figure 40). The total capacity of the tub is
4096 units with 2048 denoting empty, 0 denoting the 50% point,
and +2048 denoting full. The tub also has a safeguard to prevent
overflow. Furthermore, the tub has a low water mark at 1024
and a high water mark at +1024. To change the water level, the
user adds water with a fill bucket or removes water with a drain
bucket. The user specifies the size of the fill and drain buckets via
the 8-bit fill rate and drain rate values in the profile registers.
The phase lock detector uses the water level in the tub to determine
the lock and unlock conditions. When the water level is below
the low water mark (1024), the detector indicates an unlock
condition. Conversely, when the water level is above the high
water mark (+1024), the detector indicates a lock condition.
When the water level is between the marks, the detector holds its
last condition. This concept appears graphically in Figure 40, with
an overlay of an example of the instantaneous water level (vertical)
vs. time (horizontal) and the resulting lock/unlock states.
0
2048
–2048
1024
–1024
LOCK LEVEL
UNLOCK LEVEL
LOCKED
UNLOCKED
PREVIOUS
STATE
FILL
RATE
DRAIN
RATE
0
83
00-
017
Figure 40. Phase Lock Detector Diagram
During any given PFD phase error sample, the detector either adds
water with the fill bucket or removes water with the drain bucket
(one or the other but not both). The decision on whether to add or
remove water depends on the threshold level specified by the user.
The phase lock threshold value is a 16-bit number stored in the
profile registers and carries units of picoseconds (ps). Thus, the
phase lock threshold extends from 0 ns to ±65.535 ns and repre-
sents the magnitude of the phase error at the output of the PFD.
The phase lock detector compares each phase error sample at the
output of the PFD to the programmed phase threshold value. If the
absolute value of the phase error sample is less than or equal to
the programmed phase threshold value, the detector control logic
dumps one fill bucket into the tub. Otherwise, it removes one
drain bucket from the tub. Note that it is not the polarity of the
相關(guān)PDF資料
PDF描述
D38999/20MF11JN CONN RCPT 11POS WALL MNT W/SCKT
AD9549ABCPZ IC CLOCK GEN/SYNCHRONIZR 64LFCSP
ADN2814ACPZ IC CLOCK/DATA RECOVERY 32LFCSP
SM802105UMG IC SYNTHESIZER 2CH 24-QFN
SM802104UMG IC SYNTHESIZER 2CH 24-QFN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9547BCPZ-REEL7 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
AD9548 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad/Octal Input Network Clock Generator/Synchronizer
AD9548/PCBZ 功能描述:BOARD EVAL FOR AD9548 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9548/PCBZ 制造商:Analog Devices 功能描述:Clock Generator Evaluation Board
AD9548BCPZ 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*