- 您現(xiàn)在的位置：買賣IC網 > PDF目錄9673 > AD9547BCPZ (Analog Devices Inc)IC CLOCK GEN/SYNCHRONIZR 64LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9547BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 34/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產品變化通告： | AD9547 Mask Change 20/Oct/2010 |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁
Data Sheet
AD9547
Rev. E | Page 35 of 104
DDS Phase Offset
The relative phase of the sinusoid generated by the DDS is numer-
ically controlled by adding a phase offset word to the output of the
DDS accumulator. This is accomplished via the open loop phase
offset register (Address 0x030D to Address 0x030E), which is a
programmable 16-bit value (Δphase). The resulting phase offset,
ΔΦ (radians), is given by
16
2
phase
Φ
Phase offset and relative time offset are directly related. The
time offset is (phase/216)/fDDS (seconds), where fDDS is the
output frequency of the DDS (Hz).
DAC Output
The output of the digital core of the DDS is a time series of
numbers representing a sinusoidal waveform. The DAC
translates the numeric values to an analog signal. The DAC
output signal appears at two pins that constitute a balanced
current source architecture (see Figure 42).
CURRENT
SWITCH
ARRAY
SWITCH
CONTROL
IFS
ISCALE
AVDD3
DACOUTP
DACOUTN
CURRENT
MIRROR
GND
16
GND
13
14
CODE
50
14
10
IFS 1–
214 – 1
CODE
IFS
214 – 1
08
300-
019
Figure 42. DAC Output Pins
The value of IFS is programmable via the 10-bit DAC full-scale
current word in the DAC current register (Address 0x0213 and
Address 0x0214). The value of the 10-bit word (ISCALE) sets IFS
according to the following formula:
IFS
= 120 μA × (72 +
16
3
× ISCALE)
TUNING WORD PROCESSING
The frequency tuning words that dictate the output frequency
of the DDS come from one of three sources (see Figure 43).
The free-running frequency tuning word register
The output of the digital loop filter
The output of the tuning word history processor
TUNING WORD
HISTORY
PROCESSOR
TUNING WORD
HISTORY
FREE-RUN
TUNING WORD
UPDATE
FROM DIGITAL
LOOP FILTER
TO DDS
TUNING
WORD
ROUTING
CONTROL
TUNING
WORD
CLAMP
LOWER
TUNING
WORD
UPPER
TUNING
WORD
0830
0-
070
Figure 43. Tuning Word Processing
When the DPLL is in free-run mode, the DDS tuning word
is the value stored in the free-running frequency tuning word
register (Address 0x0300 to Address 0x0305). When the DPLL
is operating normally (closed loop), the DDS tuning word comes
from the output of the digital loop filter, which changes dynami-
cally to maintain phase lock with the input reference signal
(assuming that the device has not performed an automatic switch
to holdover mode). When the DPLL is in holdover mode, the DDS
tuning word depends on a historical record of past tuning words
during the time that the DPLL operated in closed-loop mode.
However, regardless of the operating mode, the DDS output
frequency is ultimately subject to the boundary conditions
imposed by the frequency clamp logic as explained in the
Frequency Clamp section.
Frequency Clamp
The user controls the frequency clamp boundaries via the pull-
in range limit registers (Address 0x0307 to Address 0x030C).
These registers allow the user to fix the DDS output frequency
between an upper and lower bound with a granularity of 24 bits.
Note that these upper and lower bounds apply regardless of the
frequency tuning word that appears at the input to the DDS.
The register value relates to the absolute upper or lower
frequency bound (fCLAMP) as
fCLAMP
= fS × (N/224)
where N is the value stored in the upper- or lower-limit register,
and fS is the system sample rate.
Even though the frequency clamp limits put a bound on the
DDS output frequency, the DPLL is still free to steer the DDS
frequency within the clamp limits. The default register values
set the clamp range from 0 Hz (dc) to fS, effectively eliminating
the frequency clamp functionality until the user alters the
register values.
Frequency Tuning Word History
The AD9547 has the ability to track the history of the tuning
word samples generated by the DPLL digital loop filter output.
It does so by periodically computing the average tuning word
value over a user specified interval. The user programs the
interval via the 24-bit history accumulation timer register
(Address 0x0318 to Address 0x031A). This 24-bit value repre-
sents a time interval (TAVG) in units of milliseconds (ms) that
extends from 1 ms to a maximum of 4:39:37.215 (hr:min:sec).
相關PDF資料 |
PDF描述 |
|---|---|
| D38999/20MF11JN | CONN RCPT 11POS WALL MNT W/SCKT |
| AD9549ABCPZ | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| ADN2814ACPZ | IC CLOCK/DATA RECOVERY 32LFCSP |
| SM802105UMG | IC SYNTHESIZER 2CH 24-QFN |
| SM802104UMG | IC SYNTHESIZER 2CH 24-QFN |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9547BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| AD9548 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad/Octal Input Network Clock Generator/Synchronizer |
| AD9548/PCBZ | 功能描述:BOARD EVAL FOR AD9548 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9548/PCBZ | 制造商:Analog Devices 功能描述:Clock Generator Evaluation Board |
| AD9548BCPZ | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
發(fā)布緊急采購，3分鐘左右您將得到回復。