參數(shù)資料
型號(hào)： AD9547BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 13/104頁
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9547 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
AD9547
Data Sheet
Rev. E | Page 16 of 104
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
20
I
Differential
CLKINN
Clock DistributionInput. In standard operating mode, this pin is connected to
the filteredDACOUTNoutput.Thisinternally biasedinputis typically ac-coupled,
and, when configured as such, can accept any differential signal with a single-
ended swing of at least 400 mV.
21
I
Differential
input
CLKINP
Clock DistributionInput. In standard operating mode, this pin is connected to
the filteredDACOUTP output.
23
I
Power
AVDD
1.8 V Analog (Input Receiver) Power Supply.
24
O
Current set
resistor
OUT_RSET
Connect an optional 3.12 k resistor from this pin to ground (see the Output
25, 31
I
Power
AVDD3
Analog Supply for Output Driver. These pins are normally 3.3 V but can be
1.8 V. Pin 25 powers OUT0. Pin 31 powers OUT1. Apply power to these pins
even if the corresponding outputs (OUT0P/OUT0N, OUT1P/OUT1N) are not
used. See the Power Supply Partitions section.
26
O
LVPECL,
LVDS, or
CMOS
OUT0P
Output 0. This output can be configured as LVPECL, LVDS, or single-ended
CMOS. LVPECL and LVDS operationrequire a 3.3 V output driver power
supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output
driver power supply.
27
O
LVPECL,
LVDS, or
CMOS
OUT0N
Complementary Output 0. This output can be configured as LVPECL, LVDS, or
single-ended CMOS.
28, 32
I
Power
AVDD
1.8 V Analog (Output Divider) Power Supply.
29
O
LVPECL,
LVDS, or
CMOS
OUT1P
Output 1. This output can be configured as LVPECL, LVDS, or single-ended
CMOS. LVPECL and LVDS operationrequire a 3.3 V output driver power
supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output
driver power supply.
30
O
LVPECL,
LVDS, or
CMOS
OUT1N
Complementary Output 1. This output can be configured as LVPECL, LVDS, or
single-ended CMOS.
33
I
Power
AVDD3
3.3 V Analog (System Clock) Power Supply.
34
I
SYSCLK_VREG
System Clock Loop Filter Voltage Regulator. Connect a 0.1 μF capacitor from
this pinto ground. This pinis also the ac ground reference for the integrated
externalloopfilter ofthe SYSCLK PLL multiplier(seethe SYSCLK PLL Multiplier
section).
35
O
SYSCLK_LF
System Clock Multiplier Loop Filter. Whenusing the frequency multiplier to
drive the system clock, an external loop filter can be attached to this pin.
36, 39
I
Power
AVDD
1.8 V Analog (System Clock) Power Supply.
37
I
Differential
input
SYSCLKN
Complementary System Clock Input. Complementary signal to SYSCLKP.
SYSCLKN containsinternaldc biasingandshouldbe ac-coupledwitha 0.01μF
capacitor, except when using a crystal. When using a crystal, connect it across
SYSCLKP and SYSCLKN.
38
I
Differential
input
SYSCLKP
System Clock Input. SYSCLKP contains internal dc biasing and should be ac-
coupledwith a 0.01 μF capacitor, except when using a crystal. When using a
crystal, connect it directly across SYSCLKP and SYSCLKN. Single-ended 1.8 V
CMOS is also an option but can introduce a spur if the doubler is enabledand
the duty cycle is not 50%. When using SYSCLKP as a single-ended input,
connect a 0.01 μF capacitor from SYSCLKN to ground.
40, 41
I
TDC_VRB,
TDC_VRT
Use capacitive decouplingon these pins (see Figure 37).
42
I
Power
AVDD
1.8 V Analog (Time-to-Digital Converter) Power Supply.
43, 49
I
Power
AVDD3
3.3 V Analog (Reference Input) Power Supply.
44
I
Differential
input
REFA
Reference A Input. This internally biased input is typically ac-coupledand,
when configured as such, can accept any differential signal with a single-
endedswingofup to 3.3 V. Ifdc-coupled,input canbeLVPECL, CMOS,or LVDS.
45
I
Differential
input
REFAA
Complementary Reference A Input. Complementary signal to the input pro-
videdonPin44. The usercanconfigurethis pinas a separatesingle-endedinput.
46, 50
I
Power
AVDD
1.8 V Analog (Reference Input) Power Supply.
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