參數(shù)資料
型號(hào)： AD9547BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 33/104頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9547 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤(pán)
AD9547
Data Sheet
Rev. E | Page 34 of 104
phase error sample but, rather, its magnitude relative tothe phase
threshold value that determines whether to fill or drain. If more
filling is taking place than draining, the water level in the tub
eventually rises above the high water mark (+1024), which causes
the phase lock detector toindicate lock. If more draining is taking
place than filling, the water levelin the tubeventually falls below
the low water mark (1024), which causes the phase lock detector
to indicate unlock. The ability to specify the threshold level, fill
rate, and drain rate enables the user to tailor the operation of
the phase lock detector to the statistics of the timing jitter
associated with the input reference signal.
Note that when the AD9547 enters the free-run or holdover
mode, the DPLL phase lock detector indicates unlocked. Also,
when the AD9547 performs a reference switchover, the state of
the lock detector prior to the switch is preserved during the
transition period.
DPLLFrequencyLock Detector
The operation of the frequency lock detector is identical to that
of the phase lock detector. The only difference is that the fill or
drain decision is based on the period deviation between the
reference and feedback signals of the DPLL instead of the phase
error at the output of the PFD.
The frequency lock detector uses a 24-bit frequency threshold
register specified in units of picoseconds (ps). Thus, the fre-
quency threshold value extends from 0 μs to ±16.777215 μs.
It represents the magnitude of the difference in period between
the reference and feedback signals at the input to the DPLL. For
example, if the reference signal is 1.25 MHz and the feedback
signal is 1.38 MHz, the period difference is approximately 75.36 ns
(|1/1,250,000 1/1,380,000| ≈ 75.36 ns).
DIRECT DIGITAL SYNTHESIZER (DDS)
DDS Overview
One of the primary building blocks of the digital PLL is a direct
digital synthesizer (DDS). The DDS behaves like a sinusoidal
signal generator. The frequency of the sinusoid generated by the
DDS is determined by a frequency tuning word (FTW), which
is a digital (that is, numeric) value. Unlike an analog sinusoidal
generator, a DDS uses digital building blocks and operates as a
sampled system. Thus, it requires a sampling clock (fS) that serves
as the fundamental timing source of the DDS. The accumulator
behaves as a modulo-248 counter with a programmable step size
(FTW). A block diagram of the DDS appears in Figure 41.
The input to the DDS is the 48-bit FTW. The FTW serves as
a step size value. On each cycle of fS, the accumulator adds the
value of the FTW to the running total at its output. For example,
given that FTW = 5, the accumulator counts by fives, incre-
menting on each fS cycle. Over time, the accumulator reaches
the upper end of its capacity (248 in this case), at which point,
it rolls over but retains the excess. The average rate at which the
accumulator rolls over establishes the frequency of the output
sinusoid. The average rollover rate of the accumulator establishes
the output frequency (fDDS) of the DDS and is given by
S
DDS
f
FTW
f
=
48
2
Solving this equation for FTW yields
=
S
DDS
f
FTW
48
2
round
For example, given that fS = 1 GHz and fDDS = 155.52 MHz, then
FTW = 43,774,988,378,041 (0x27D028A1DFB9).
Note that the minimum DAC output frequency is 62.5 MHz;
therefore, normal operation requires an FTW that yields an
output frequency in excess of this lower bound.
DAC
(14-BIT)
PHASE
OFFSET
Q
D
fS
FREQUENCY
TUNING WORD
(FTW)
DAC+
DAC–
14
19
48
19
ANGLE TO
AMPLITUDE
CONVERSION
48
48-BIT ACCUMULATOR
16
08300-
018
Figure 41. DDS Block Diagram
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參數(shù)描述
AD9547BCPZ-REEL7 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類(lèi)型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
AD9548 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Quad/Octal Input Network Clock Generator/Synchronizer
AD9548/PCBZ 功能描述:BOARD EVAL FOR AD9548 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9548/PCBZ 制造商:Analog Devices 功能描述:Clock Generator Evaluation Board
AD9548BCPZ 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱(chēng):296-6719-6
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