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參數(shù)資料
| 型號： | HC805P18GRS |
| 英文描述： | 68HC805P18 Technical Data |
| 中文描述： | 68HC805P18技術(shù)數(shù)據(jù) |
| 文件頁數(shù)： | 16/111頁 |
| 文件大?。?/td> | 748K |
| 代理商： | HC805P18GRS |
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GENERAL RELEASE SPECIFICATION
MC68HC805P18
Rev. 1.0
INTRODUCTION
MOTOROLA
1-7
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
1.4.6 Port B (PB5/SDO, PB6/SDI, and PB7/SCK)
These three I/O pins comprise port B and are shared with the SIOP
communications subsystem. The state of any pin is software programmable and all
port B lines are configured as inputs during power-on or reset. For further
information, refer to
SECTION 7 INPUT/OUTPUT PORTS
and
SECTION 11
SERIAL INPUT/OUTPUT PORT
.
1.4.7 Port C (PC0–PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/V
REFH
)
These eight I/O pins comprise port C and are shared with the A/D converter
subsystem. The state of any pin is software programmable and all port C lines are
configured as inputs during power-on or reset. Port pins PC0 and PC1 are capable
of sourcing and sinking high currents. For further information, refer to
SECTION 7
INPUT/OUTPUT PORTS
and
SECTION 9 ANALOG-TO-DIGITAL CONVERTER
.
1.4.8 Port D (PD5/CKOUT and PD7/TCAP)
These two I/O pins comprise port D, and one of them is shared with the 16-bit timer
subsystem. The state of PD5/CKOUT is software programmable and is configured
as an input during power-on or reset (unless clock output has been selected). PD7
is always an input; it may be read at any time, regardless of the mode of operation
the 16-bit timer may be in. For further information, refer to
SECTION 7
INPUT/OUTPUT PORTS
and
SECTION 10 16-BIT TIMER
. The PD5/CKOUT pin
can be turned into a clock output pin by programming mask option register 1. Clock
output is a buffered OSC2 signal with a CMOS output driver.
1.4.9 TCMP
This pin is the output from the 16-bit timer’s output compare function. It is low after
reset. For further information, refer to
SECTION 10 16-BIT TIMER
.
1.4.10 Maskable Interrupt Request (IRQ)
This input pin drives the asynchronous interrupt function of the MCU. The MCU will
complete the current instruction being executed before it responds to the IRQ
interrupt request. When IRQ is driven low, the event is latched internally to signify
an interrupt has been requested. When the MCU completes its current instruction,
the interrupt latch is tested. If the interrupt latch is set and the interrupt mask bit
(I bit) in the condition code register is clear, the MCU will begin the interrupt
sequence.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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