參數(shù)資料
型號： HC805P18GRS
英文描述： 68HC805P18 Technical Data
中文描述： 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù)： 36/111頁
文件大小： 748K
代理商： HC805P18GRS
GENERAL RELEASE SPECIFICATION
MC68HC805P18
Rev. 1.0
RESETS
MOTOROLA
5-3
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
5.3.3 Low-Voltage Reset (LVR)
If the LVR has been enabled via MOR1, the internal LVR reset is generated when
the supply voltage to the V
DD
pin falls below a nominal 3.80 Vdc. The LVR
threshold is not intended to be an accurate and stable trip point, but is intended to
ensure that the CPU will be held in reset when the V
DD
supply voltage is below
reasonable operating limits. If the LVR is tripped for a short time, the LVR reset
signal will last at least two cycles of the CPU bus clock, PH2.
The LVR will generate the RST signal which will reset the CPU and other
peripherals. Also, the LVR will establish the mode of operation based on the state
of the IRQ pin at the time the LVR signal ends. If any other reset function is active
at the end of the LVR reset signal, the RST signal will remain in the reset condition
until the other reset condition(s) end.
NOTE
The voltage of the IRQ pin must be between 0–V
DD
volts to stay in
the normal operation mode.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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