參數(shù)資料
型號: HC805P18GRS
英文描述: 68HC805P18 Technical Data
中文描述: 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù): 71/111頁
文件大?。?/td> 748K
代理商: HC805P18GRS
GENERAL RELEASE SPECIFICATION
MC68HC805P18
Rev. 1.0
16-BIT TIMER
MOTOROLA
10-9
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
After a read of the MSB of the input capture register pair (ICRH), counter transfers
are inhibited until the LSB of the register pair (ICRL) is also read. This characteristic
forces the minimum pulse period attainable to be determined by the time required
to execute an input capture software routine in an application.
Reading the LSB of the input capture register pair (ICRL) does not inhibit transfer
of the free-running counter. Again, minimum pulse periods are ones which allow
software to read the LSB of the register pair (ICRL) and perform needed
operations. There is no conflict between reading the LSB (ICRL) and the
free-running counter transfer, since they occur on opposite edges of the PH2 clock.
Figure 10-9. State Timing Diagram for Input Capture
INPUT
CAPTURE
FLAG
INPUT
CAPTURE
REGISTER
16-BIT
FREE-RUNNING
COUNTER
TCAP
PIN
INPUT
CAPTURE
LATCH
PH2
CLOCK
NOTE: If the input edge occurs in the shaded area from one T10 timer state to the other T10 timer state, the input capture
flag is set during the next T11 timer state.
$FFEC
$FFED
$FFEE
$FFEF
$FFEB
$
$FFED
(SEE NOTE)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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