參數(shù)資料
型號(hào)： HC805P18GRS
英文描述： 68HC805P18 Technical Data
中文描述： 68HC805P18技術(shù)數(shù)據(jù)
文件頁(yè)數(shù)： 45/111頁(yè)
文件大小： 748K
代理商： HC805P18GRS
GENERAL RELEASE SPECIFICATION
MC68HC805P18
Rev. 1.0
INPUT/OUTPUT PORTS
MOTOROLA
7-1
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
SECTION 7
INPUT/OUTPUT PORTS
7.1 Introduction
In user mode, 20 bidirectional input/output (I/O) lines are arranged as two 8-bit I/O
ports (ports A and C), one 3-bit I/O port (port B), and one 1-bit I/O port (port D).
These ports are programmable as either inputs or outputs under software control
of the data direction registers (DDRs). An input-only pin is associated with port D.
7.2 Port A
Port A is an 8-bit bidirectional port which can share its pins with the IRQ interrupt
system as shown in Figure 7-1. Each port A pin is controlled by the corresponding
bits in a data direction register and a data register. The port A data register is
located at address $0000. The port A data direction register (DDRA) is located at
address $0004. Reset clears the DDRA, thereby initializing port A as an input port.
The port A data register is unaffected by reset.
Figure 7-1. Port A I/O Circuitry
READ $0000
WRITE $0000
READ $0004
DATA
REGISTER BIT
TO IRQ INTERRUPT
SYSTEM
I/O
PIN
OUTPUT
INTERNAL HC05
DATA BUS
RESET
(RST)
WRITE $0004
DATA DIRECTION
REGISTER BIT
MOR 2
100
μ
A
PULLUP
V
DD
(PULLUP INHIBIT)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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