參數(shù)資料
型號(hào)： HC805P18GRS
英文描述： 68HC805P18 Technical Data
中文描述： 68HC805P18技術(shù)數(shù)據(jù)
文件頁(yè)數(shù)： 48/111頁(yè)
文件大小： 748K
代理商： HC805P18GRS
GENERAL RELEASE SPECIFICATION
MOTOROLA
7-4
INPUT/OUTPUT PORTS
MC68HC805P18
Rev. 1.0
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
7.5 Port D
Port D is a 2-bit port with one bidirectional pin (PD5/CKOUT) and one input-only
pin (PD7). Pin PD7 is shared with the 16-bit timer. PD5 can be replaced with a
buffered OSC2 clock output via MOR1. The port D data register is located at
address $0003 and its data direction register (DDR) is located at address $0007.
Reset does not affect the data registers, but clears the DDRs, thereby setting
PD5/CKOUT to input mode. Writing a one to DDR bit 5 sets PD5/CKOUT to output
mode (see Figure 7-4).
Port D may be used for general I/O applications regardless of the state of the 16-bit
timer. Since PD7 is an input-only line, its state can be read from the port D data
register at any time.
Figure 7-4. Port D I/O Circuitry
DATA
REGISTER BIT
DATA DIRECTION
REGISTER BIT
READ $0003
WRITE $0003
READ $0007
I/O
PIN
OUTPUT
INTERNAL HC05
DATA BUS
RESET
(RST)
WRITE $0007
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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