參數(shù)資料
型號: HC805P18GRS
英文描述: 68HC805P18 Technical Data
中文描述: 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù): 81/111頁
文件大?。?/td> 748K
代理商: HC805P18GRS
GENERAL RELEASE SPECIFICATION
MC68HC805P18
Rev. 1.0
INSTRUCTION SET
MOTOROLA
12-1
SECTION 12
INSTRUCTION SET
12.1 Introduction
This section describes the addressing modes and instruction types.
12.2 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The
addressing modes define the manner in which the CPU finds the data required to
execute an instruction. The eight addressing modes are:
Inherent
Immediate
Direct
Extended
Indexed, no offset
Indexed, 8-bit offset
Indexed, 16-bit offset
Relative
12.2.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent
instructions require no memory address and are one byte long.
12.2.2 Immediate
Immediate instructions are those that contain a value to be used in an operation
with the value in the accumulator or index register. Immediate instructions require
no memory address and are two bytes long. The opcode is the first byte, and the
immediate data value is the second byte.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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