參數(shù)資料
型號: HC805P18GRS
英文描述: 68HC805P18 Technical Data
中文描述: 68HC805P18技術數(shù)據(jù)
文件頁數(shù): 34/111頁
文件大?。?/td> 748K
代理商: HC805P18GRS
GENERAL RELEASE SPECIFICATION
MC68HC805P18
Rev. 1.0
RESETS
MOTOROLA
5-1
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
SECTION 5
RESETS
5.1 Introduction
The MCU can be reset from four sources: one external input and three internal
reset conditions. The RESET pin is an input with a Schmitt trigger as shown in
Figure 5-1. The CPU and all peripheral modules will be reset by the RST signal
which is the logical OR of internal reset functions and is clocked by PH2.
5.2 External Reset (RESET)
The RESET input is the only external reset and is connected to an internal Schmitt
trigger. The external reset occurs whenever the RESET input is driven below the
lower threshold and remains in reset until the RESET pin rises above the upper
threshold. The upper and lower thresholds are given in
SECTION 13
ELECTRICAL SPECIFICATIONS
.
Figure 5-1. Reset Block Diagram
CPU
LATCH
RESET
COP WATCHDOG
(COPR)
RST
OSC
DATA
ADDRESS
PH2
TO OTHER
PERIPHERALS
S
LOW-VOLTAGE
RESET (LVR)
V
DD
IRQ
MODE
SELECT
TO IRQ
LOGIC
LATCH
R
POWER-ON RESET
(POR)
V
DD
PH2
CLOCKED
ONE-SHOT
(PULSE WIDTH =4 xE-CLK)
D
D
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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