參數(shù)資料
型號: HC805P18GRS
英文描述: 68HC805P18 Technical Data
中文描述: 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù): 78/111頁
文件大?。?/td> 748K
代理商: HC805P18GRS
GENERAL RELEASE SPECIFICATION
MOTOROLA
11-4
SERIAL INPUT/OUTPUT PORT
MC68HC805P18
Rev. 1.0
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
11.3.1 SIOP Control Register (SCR)
This register is located at address $000A and contains two bits. Figure 11-3 shows
the position of each bit in the register and indicates the value of each bit after reset.
SPE — Serial Peripheral Enable
When set, the SPE bit enables the SIOP subsystem such that SDO/PB5 is the
serial data output, SDI/PB6 is the serial data input, and SCK/PB7 is a serial
clock input in the slave mode or a serial clock output in the master mode. Port
B DDR and data registers can be manipulated as usual (except for PB5);
however, these actions could affect the transmitted or received data.
The SPE bit is readable and writable at any time. Clearing the SPE bit while a
transmission is in progress will 1) abort the transmission, 2) reset the serial bit
counter, and 3) convert the port B/SIOP port to a general-purpose I/O port.
Reset clears the SPE bit.
MSTR — Master Mode Select
When set, the MSTR bit configures the serial I/O port for master mode. A
transfer is initiated by writing to the SDR. Also, the SCK pin becomes an output
providing a synchronous data clock dependent upon the oscillator frequency.
When the device is in slave mode, the SDO and SDI pins do not change
function. These pins behave exactly the same in both the master and slave
modes.
The MSTR bit is readable and writable at any time regardless of the state of the
SPE bit. Clearing the MSTR bit will abort any transfers that may have been in
progress. Reset clears the MSTR bit, placing the SIOP subsystem in slave
mode.
Bit 7
6
5
4
3
2
1
Bit 0
SCR
$000A
Read:
0
SPE
0
MSTR
0
0
0
0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-3. SIOP Control Register
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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