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參數(shù)資料
| 型號： | HC805P18GRS |
| 英文描述： | 68HC805P18 Technical Data |
| 中文描述： | 68HC805P18技術(shù)數(shù)據(jù) |
| 文件頁數(shù)： | 44/111頁 |
| 文件大?。?/td> | 748K |
| 代理商： | HC805P18GRS |
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GENERAL RELEASE SPECIFICATION
MOTOROLA
6-8
OPERATING MODES
MC68HC805P18
Rev. 1.0
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
6.4.3 WAIT Instruction
The WAIT instruction places the MCU in a low-power mode which consumes more
power than the stop mode. In wait mode the PH2 clock is halted, suspending all
processor and internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer and reset to be generated from the
COP watchdog timer. Execution of the WAIT instruction automatically clears the I
bit in the condition code register enabling the IRQ external interrupt. All other
registers, memory, and input/output lines remain in their previous state.
If the 16-bit timer interrupt is enabled it will cause the processor to exit the wait
mode and resume normal operation. The 16-bit timer may be used to generate a
periodic exit from the wait mode. The wait mode may also be exited when an IRQ
or RESET occurs. Note that if port A interrupts (if programmed as an option in the
mask option register 1) will also exit wait mode. However, when exiting the wait
mode, the internal oscillator will not need to wait for 4064 PH2 clock cycles to
stabilize as in the stop and halt modes.
6.5 COP Watchdog Timer Considerations
The COP watchdog timer is active in user mode of operation when programmed
as an option in MOR1. Executing the STOP instruction without conversion to halt
(via mask option register1) will cause the COP to be disabled. Therefore, it is
recommended that the STOP instruction be modified to produce halt mode (via
MOR1) if the COP watchdog timer will be enabled.
Furthermore, it is recommended that the COP watchdog timer be disabled for
applications that will use the halt or wait modes for time periods that will exceed the
COP time-out period.
COP watchdog timer interactions are summarized in Table 6-3.
Table 6-3. COP Watchdog Timer Recommendations
IF the following conditions exist:
THEN the COP Watchdog
Timer should be:
STOP Instruction Mode
Wait Period
Halt Mode Selected
via MOR1, Bit 5
WAIT Period Less than
COP Time Out
Enable or Disable COP
via MOR1, Bit 0
Halt Mode Selected
via MOR1, Bit 5
WAIT Period More Than
COP Time Out
Disable COP
via MOR1, Bit 0
Stop Mode Selected
via MOR1, Bit 5
Any Length Wait Period
Disable COP
via MOR1, Bit 0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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