參數(shù)資料
型號： HC805P18GRS
英文描述： 68HC805P18 Technical Data
中文描述： 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù)： 49/111頁
文件大?。?/td> 748K
代理商： HC805P18GRS
GENERAL RELEASE SPECIFICATION
MC68HC805P18
Rev. 1.0
INPUT/OUTPUT PORTS
MOTOROLA
7-5
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
7.6 I/O Port Programming
Each pin on ports A through port D (except pin 7 of port D) may be programmed
as an input or an output under software control as shown in Table 7-1, Table 7-2,
Table 7-3
,
and Table 7-4. The direction of a pin is determined by the state of its
corresponding bit in the associated port data direction register (DDR). A pin is
configured as an output if its corresponding DDR bit is set to a logic one. A pin is
configured as an input if its corresponding DDR bit is cleared to a logic zero.
Table 7-1. Port A I/O Functions
DDRA
I/O Pin Mode
Access to DDRA
@ $0004
Access to Data
Register @ $0000
Read/Write
Read
Write
0
Input, High Impedance
DDRA0–DDRA7
I/O Pin
*
1
Output
DDRA0–DDRA7
PA0–PA7
PA0–PA7
*Does not affect input, but stored to data register
Table 7-2. Port B I/O Functions
DDRB
I/O Pin Mode
Access to DDRA
@ $0005
Access to Data
Register @ $0001
Read/Write
Read
Write
0
Input, High Impedance
DDRB5–DDRB7
I/O Pin
*
1
Output
DDRB5–DDRB7
PB5–PB7
PB5–PB7
*Does not affect input, but stored to data register
Table 7-3. Port C I/O Functions
DDRA
I/O Pin Mode
Access to DDRA
@ $0006
Accesses to Data
Register @ $0002
Read/Write
Read
Write
0
Input, High Impedance
DDRC0–DDRC7
I/O Pin
*
1
Output
DDRC0–DDRC7
PC0–PC7
PC0–PC7
*Does not affect input, but stored to data register
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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