參數(shù)資料
型號: HC805P18GRS
英文描述: 68HC805P18 Technical Data
中文描述: 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù): 99/111頁
文件大?。?/td> 748K
代理商: HC805P18GRS
GENERAL RELEASE SPECIFICATION
MC68HC805P18
Rev. 1.0
ELECTRICAL SPECIFICATIONS
MOTOROLA
13-5
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
13.9 SIOP Timing
(V
DD
= 4.5 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= –40
°
C to +125
°
C, unless otherwise note)
Figure 13-1. SIOP Timing Diagram
Number
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
f
SIOP(M)
f
SIOP(S)
1
dc
1
1
f
OP
1
Cycle Time
Master
Slave
t
SCK(M)
t
SCK(S)
t
CYC
t
v
t
HO
t
S
t
H
1
1
1
t
CYC
2
SCK Low Time
238
ns
3
SDO Data Valid Time
200
ns
4
SDO Hold Time
0
ns
5
SDI Setup Time
100
ns
6
SDI Hold Time
100
ns
NOTES:
1. f
OP
= f
OSC
÷
2 = 2.1 MHz max; t
CYC
= 1
÷
f
OP
2. In master mode, the SCK rate is determined by the programmable option in MOR1.
SDI
SDI
SDI
SDI
SDI
SDI
SDI
BIT 7
SCK
t
6
t
1
t
5
t
3
t
4
t
2
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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