參數(shù)資料
型號： HC805P18GRS
英文描述： 68HC805P18 Technical Data
中文描述： 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù)： 31/111頁
文件大?。?/td> 748K
代理商： HC805P18GRS
GENERAL RELEASE SPECIFICATION
MOTOROLA
4-4
INTERRUPTS
MC68HC805P18
Rev. 1.0
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
programmed as an option, a port A interrupt will use the same vector. The
interrupt service routine address is specified by the contents of memory
locations $3FFA and $3FFB.
NOTE
The internal interrupt latch is cleared 9 PH2 clock cycles after the
interrupt is recognized (after location $3FFA is read). Therefore,
another external interrupt pulse could be latched during the IRQ
service routine.
NOTE
When the edge- and level-sensitive option is selected, the voltage
applied to the IRQ pin must return to the high state before the RTI
instruction in the interrupt service routine is executed.
TheIRQ pin is one source of an IRQ interrupt and a mask option can also enable
the port A pins (PA0 through PA7) to act as other IRQ interrupt sources. These
sources are all combined into a single ORing function to be latched by the IRQ
latch.
Figure 4-2. IRQ Function Block Diagram
IRQ
LATCH
R
V
DD
IRQ PIN
MASK OPTION
(IRQ LEVEL)
TO IRQ
PROCESSING
IN CPU
TO BIH & BIL
INSTRUCTION
SENSING
:
:
:
:
:
:
:
:
:
RST
IRQ VECTOR FETCH
PA7
DDRA7
PA0
DDRA0
PA0 IRQ INHIBIT
(MASK OPTION)
PA7 IRQ INHIBIT
(MASK OPTION)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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