參數(shù)資料
型號: HC805P18GRS
英文描述: 68HC805P18 Technical Data
中文描述: 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù): 27/111頁
文件大小: 748K
代理商: HC805P18GRS
GENERAL RELEASE SPECIFICATION
MOTOROLA
3-4
CENTRAL PROCESSING UNIT
MC68HC805P18
Rev. 1.0
8
2
3
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7
8
9
10
11
12
13
14
A
16
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18
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20
3.2.4 Stack Pointer (SP)
The stack pointer contains the address of the next free location on the stack.
During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer
is set to location $00FF. The stack pointer is then decremented as data is pushed
onto the stack and incremented as data is pulled from the stack.
When accessing memory, the seven most significant bits are permanently set to
0000011. These seven bits are appended to the six least significant register bits to
produce an address within the range of $00FF to $00C0. Subroutines and
interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the
stack pointer wraps around and loses the previously stored information. A
subroutine call occupies two locations on the stack; an interrupt uses five locations.
3.2.5 Program Counter (PC)
The program counter is a 13-bit register that contains the address of the next byte
to be fetched.
NOTE
The M68HC05 CPU core is capable of addressing a 64-Kbyte
memory map. For this implementation, however, the addressing
registers are limited to an 8-Kbyte memory map.
0
0
0
0
0
1
1
SP
12
7
0
PC
12
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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