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| 型號(hào)： | HC805P18GRS |
| 英文描述： | 68HC805P18 Technical Data |
| 中文描述： | 68HC805P18技術(shù)數(shù)據(jù) |
| 文件頁(yè)數(shù)： | 77/111頁(yè) |
| 文件大小： | 748K |
| 代理商： | HC805P18GRS |
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GENERAL RELEASE SPECIFICATION
MC68HC805P18
Rev. 1.0
SERIAL INPUT/OUTPUT PORT
MOTOROLA
11-3
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
11.2.2 Serial Data Input (SDI)
The SDI pin becomes an input as soon as the SIOP subsystem is enabled. New
data is presented to the SDI pin on the falling edge of SCK. Valid data must be
present at least 100 nanoseconds before the rising edge of SCK and remain valid
for 100 nanoseconds after the rising edge of SCK. See Figure 11-2.
11.2.3 Serial Data Output (SDO)
The SDO pin becomes an output as soon as the SIOP subsystem is enabled. Prior
to enabling the SIOP, PB5 can be initialized to determine the beginning state.
While the SIOP is enabled, PB5 cannot be used as a standard output since that pin
is connected to the last stage of the SIOP serial shift register. The data can be
transmitted in either MSB first format or the LSB format by programming the
MOR1.
On the first falling edge of SCK, the first data bit will be shifted out to the SDO pin.
The remaining data bits will be shifted out to the SDI pin on subsequent falling
edges of SCK. The SDO pin will present valid data at least 100 nanoseconds
before the rising edge of the SCK and remain valid for 100 nanoseconds after the
rising edge of SCK. See Figure 11-2.
11.3 SIOP Registers
The SIOP is programmed and controlled by the SIOP control register (SCR)
located at address $000A, the SIOP status register (SSR) located at address
$000B, and the SIOP data register (SDR) located at address $000C.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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