參數(shù)資料
型號(hào)： HC805P18GRS
英文描述： 68HC805P18 Technical Data
中文描述： 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù)： 32/111頁
文件大?。?/td> 748K
代理商： HC805P18GRS
GENERAL RELEASE SPECIFICATION
MC68HC805P18
Rev. 1.0
INTERRUPTS
MOTOROLA
4-5
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
Any enabled IRQ interrupt source sets the IRQ latch on the falling edge of the
IRQ pin or a port A pin if port A interrupts have been enabled. If edge-only
sensitivity is chosen by a mask option, only the IRQ latch output can activate a
request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ
interrupt sensitive to the following cases:
1.
Falling edge on theIRQ pin with all enabled port A interrupt pins at a high
level.
2.
Falling edge on any enabled port A interrupt pin with all other enabled
port A interrupt pins and the IRQ pin at a high level.
If level sensitivity is chosen, the active high state of the IRQ input can also
activate an IRQ request to the CPU to generate the IRQ interrupt sequence.
This makes the IRQ interrupt sensitive to the following cases:
1.
Low level on the IRQ pin
2.
Falling edge on theIRQ pin with all enabled port A interrupt pins at a high
level
3.
Low level on any enabled port A interrupt pin
4.
Falling edge on any enabled port A interrupt pin with all enabled port A
interrupt pins and the IRQ pin at a high level
This interrupt is serviced by the interrupt service routine located at the address
specified by the contents of $3FFA and $3FFB. The IRQ latch is automatically
cleared by entering the interrupt service routine.
Optional External Interrupts (PA0–PA7)
The IRQ interrupt can be triggered by the inputs on the PA0 through PA7 port
pins if enabled by individual mask options. With pullup enabled, each port A pin
can activate the IRQ interrupt function and the interrupt operation will be the
same as for inputs to theIRQ pin. Once enabled by mask option, each individual
port A pin can be disabled as an interrupt source if its corresponding DDR bit is
configured for output mode.
NOTE
The BIH and BIL instructions apply to the output of the logic OR
function of the enabled PA0 through PA7 interrupt pins and the IRQ
pin. The BIH and BIL instructions do not test only the state of theIRQ
pin.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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