參數(shù)資料
型號： HC805P18GRS
英文描述： 68HC805P18 Technical Data
中文描述： 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù)： 54/111頁
文件大小： 748K
代理商： HC805P18GRS
GENERAL RELEASE SPECIFICATION
MOTOROLA
8-4
EEPROM
MC68HC805P18
Rev. 1.0
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
8.4 Mask Option Registers (MOR)
The MOR consists of two EEPROM bytes located at $3F00 and $3F01. The MOR
holds the 16 option bits for:
The SIOP data format, interrupt sensitivity
COP enable/disable
SIOP clock rate
LVR enable/disable
Stop conversion to halt, pullup/interrupt enable on port A
Clock output option to replace PD5
When in the erased state, the EEPROM cells will read as logic
zeros.
These
registers are refreshed every 256
μ
s during power-on reset and every 16 ms after
the part is out of reset (assuming f
OSC
= 4 MHz).
COPEN — COP enable/disable
COPEN may be read at any time. In user mode, writing has no effect. It has to
be programmed in bootloader mode.
0 = The COP is disabled (erased state).
1 = The COP is enabled.
Bit 7
6
5
4
3
2
1
0
MOR1
$3F00
Read:
CLKOUT
LVRE
SWAIT
SPR1
SPR0
LSBF
LEVIRQ
COPEN
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 8-2. Mask Option Register 1
Bit 7
6
5
4
3
2
1
0
MOR2
$3F01
Read:
PA7PU
PA6PU
PA5PU
PA4PU
PA3PU
PA2PU
PA1PU
PA0PU
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 8-3. Mask Option Register 2
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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