參數(shù)資料
型號(hào): K5A3240YT
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM
中文描述: 多芯片封裝存儲(chǔ)器32兆位(4Mx8/2Mx16)雙銀行NOR閃存/分(512Kx8/256Kx16)全CMOS SRAM的
文件頁(yè)數(shù): 21/45頁(yè)
文件大?。?/td> 867K
代理商: K5A3240YT
MCP MEMORY
K5A3x40YT(B)C
Revision 0.0
November 2002
- 28 -
Preliminary
Alternate WE Controlled Write
NOTES: 1. Not 100% tested.
2. The duration of the Program or Erase operation varies and is calculated in the internal algorithms.
Parameter
Symbol
70ns
80ns
Unit
Min
Max
Min
Max
Write Cycle Time (1)
tWC
70
-
80
-
ns
Address Setup Time
tAS
0
-
0
-
ns
tASO
55
-
55
-
ns
Address Hold Time
tAH
45
-
45
-
ns
tAHT
0
-
0
-
ns
Data Setup Time
tDS
35
-
35
-
ns
Data Hold Time
tDH
0
-
0
-
ns
Output Enable Setup Time (1)
tOES
0
-
0
-
ns
Output Enable
Hold Time
Read (1)
tOEH1
0
-
0
-
ns
Toggle and Data Polling (1)
tOEH2
10
-
10
-
ns
CEF Setup Time
tCS
0
-
0
-
ns
CEF Hold Time
tCH
0
-
0
-
ns
Write Pulse Width
tWP
35
-
35
-
ns
Write Pulse Width High
tWPH
25
-
25
-
ns
Programming Operation
Word
tPGM
14(typ.)
s
Byte
9(typ.)
s
Accelerated Programming Operation
Word
tACCPGM
9(typ.)
s
Byte
7(typ.)
s
Block Erase Operation (2)
tBERS
0.7(typ.)
sec
VccF Set Up Time
tVCS
50
-
50
-
s
Write Recovery Time from RY/BY
tRB
0
-
0
-
ns
RESET High Time Before Read
tRH
50
-
50
-
ns
RESET to Power Down Time
tRPD
20
-
20
-
s
Program/Erase Valid to RY/BY Delay
tBUSY
90
-
90
-
ns
VID Rising and Falling Time
tVID
500
-
500
-
ns
RESET Pulse Width
tRP
500
-
500
-
ns
RESET Low to RY/BY High
tRRB
-
20
-
20
s
RESET Setup Time for Temporary Unprotect
tRSP
1
-
1
-
s
RESET Low Setup Time
tRSTS
500
-
500
-
ns
RESET High to Address Valid
tRSTW
200
-
200
-
ns
Read Recovery Time Before Write
tGHWL
0
-
0
-
ns
CE High during toggling bit polling
tCEPH
20
-
20
-
ns
OE High during toggling bit polling
tOEPH
20
-
20
-
ns
Write(Erase/Program)Operations
Flash AC CHARACTERISTICS
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