參數(shù)資料
型號: K5A3240YT
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM
中文描述: 多芯片封裝存儲器32兆位(4Mx8/2Mx16)雙銀行NOR閃存/分(512Kx8/256Kx16)全CMOS SRAM的
文件頁數(shù): 30/45頁
文件大?。?/td> 867K
代理商: K5A3240YT
MCP MEMORY
K5A3x40YT(B)C
Revision 0.0
November 2002
- 36 -
Preliminary
Read While Write Operations
Flash SWITCHING WAVEFORMS
Parameter
Symbol
70ns
80ns
Unit
Min
Max
Min
Max
Write Cycle Time
tWC
70
-
80
-
ns
Write Pulse Width
tWP
35
-
35
-
ns
Write Pulse Width High
tWPH
25
-
25
-
ns
Address Setup Time
tAS
0
-
0
-
ns
Address Hold Time
tAH
45
-
45
-
ns
Data Setup Time
tDS
35
-
35
-
ns
Data Hold Time
tDH
0
-
0
-
ns
Read Cycle Time
tRC
70
-
80
-
ns
Chip Enable Access Time
tCE
-
70
-
80
ns
Address Access Time
tAA
-
70
-
80
ns
Output Enable Access Time
tOE
-
25
-
25
ns
OE Setup Time
tOES
0
-
0
-
ns
OE Hold Time
tOEH2
10
-
10
-
ns
CEF & OE Disable Time
tDF
-
16
-
16
ns
Address Hold Time
tAHT
0
-
0
-
ns
CEF High during toggle bit polling
tCEPH
20
-
20
-
ns
NOTE: This is an example in the program-case of the Read While Write function.
DA1 : Address of Bank1, DA2 : Address of Bank 2
PA = Program Address at one bank , RA = Read Address at the other bank, PD = Program Data In , RD = Read Data Out
OE
CEF
DQ
WE
tRC
Read
Command
Read
tAH
tAA
tCE
tAS
tAHT
tAS
tCEPH
tOE
tOES
tWP
tOEH2
tDF
tDS
tDH
tDF
DA1
DA2
DA1
DA2
(555H)
(PA)
Valid
Output
Valid
Output
Valid
Input
Valid
Output
Valid
Input
Status
Address
(A0H)
(PD)
tRC
tWC
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