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參數(shù)資料
| 型號： | K5A3240YT |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM |
| 中文描述： | 多芯片封裝存儲器32兆位（4Mx8/2Mx16）雙銀行NOR閃存/分（512Kx8/256Kx16）全CMOS SRAM的 |
| 文件頁數(shù)： | 39/45頁 |
| 文件大小： | 867K |
| 代理商： | K5A3240YT |
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MCP MEMORY
K5A3x40YT(B)C
Revision 0.0
November 2002
- 44 -
Preliminary
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1S and low WE. A write begins when CS1S goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS1S goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1S going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1S or WE going high.
tWC
tCW(2)
tBW
tWP(1)
tDH
tDW
tWR(4)
tAW
SRAM DATA RETENTION WAVE FORM
CS1S controlled
VccS
2.7V
2.2V
VDR
CS1S
Vss
Data Retention Mode
CS1S≥VccS - 0.2V
tSDR
tRDR
tAS(3)
CS1S
CS2S
CS2S controlled
VccS
2.7V
0.4V
VDR
CS2S
Vss
Data Retention Mode
tSDR
tRDR
CS2S≤0.2V
tCW(2)
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相關(guān)代理商/技術(shù)參數(shù) |
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| K5A3240YTC-T755 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM |
| K5A3240YTC-T855 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM |
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