參數(shù)資料
型號: K5A3240YT
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM
中文描述: 多芯片封裝存儲器32兆位(4Mx8/2Mx16)雙銀行NOR閃存/分(512Kx8/256Kx16)全CMOS SRAM的
文件頁數(shù): 37/45頁
文件大?。?/td> 867K
代理商: K5A3240YT
MCP MEMORY
K5A3x40YT(B)C
Revision 0.0
November 2002
- 42 -
Preliminary
SRAM TIMING DIAGRAMS
Address
Data Out
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1
S=OE=VIL, CS2S=WE=VIH, UB or/and LB=VIL)
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Data Valid
High-Z
tRC
CS1S
Address
UB, LB
OE
Data out
tAA
tRC
tOH
tAA
tCO1
tBA
tOE
tOLZ
tBLZ
tLZ
tOHZ
tBHZ
tHZ
NOTES (READ CYCLE)
1.
tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
CS2S
tCO2
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