參數(shù)資料
型號: K5A3240YT
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM
中文描述: 多芯片封裝存儲器32兆位(4Mx8/2Mx16)雙銀行NOR閃存/分(512Kx8/256Kx16)全CMOS SRAM的
文件頁數(shù): 36/45頁
文件大?。?/td> 867K
代理商: K5A3240YT
MCP MEMORY
K5A3x40YT(B)C
Revision 0.0
November 2002
- 41 -
Preliminary
SRAM DATA RETENTION CHARACTERISTICS
1. CS1S≥VccS-0.2V, CS2S≥VccS-0.2V(CS1S controlled) or CS2S≤0.2V(CS2S controlled)
2. Typical values are measured at Vcc=3.0V, Ta=25
°C , not 100% tested.
Item
Symbol
Test Condition
Min
Typ
Max
Unit
VccS for data retention
VDR
CS1S≥VccS-0.2V
1.5
-
3.3
V
Data retention current
IDR
VccS=3.0V, CS1S≥VccS-0.2V
-
0.5
10
A
Data retention set-up time
tSDR
See data retention waveform
0
-
ns
Recovery time
tRDR
tRC
-
SRAM AC CHARACTERISTICS
Parameter List
Symbol
55ns
Units
Min
Max
Read
Read cycle time
tRC
55
-
ns
Address access time
tAA
-
55
ns
Chip select to output
tCO1, tCO2
-
55
ns
Output enable to valid output
tOE
-
25
ns
UB, LB Access Time
tBA
-
55
ns
Chip select to low-Z output
tLZ1, tLZ2
10
-
ns
UB, LB enable to low-Z output
tBLZ
10
-
ns
Output enable to low-Z output
tOLZ
5
-
ns
Chip disable to high-Z output
tHZ1, tHZ2
0
20
ns
UB, LB disable to high-Z output
tBHZ
0
20
ns
Output disable to high-Z output
tOHZ
0
20
ns
Output hold from address change
tOH
10
-
ns
Write
Write cycle time
tWC
55
-
ns
Chip select to end of write
tCW
45
-
ns
Address set-up time
tAS
0
-
ns
Address valid to end of write
tAW
45
-
ns
UB, LB Valid to End of Write
tBW
45
-
ns
Write pulse width
tWP
40
-
ns
Write recovery time
tWR
0
-
ns
Write to output high-Z
tWHZ
0
20
ns
Data to write time overlap
tDW
20
-
ns
Data hold from write time
tDH
0
-
ns
End write to output low-Z
tOW
5
-
ns
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