參數(shù)資料
型號(hào)： LXT972A
廠商： Intel Corp.
英文描述： 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
中文描述： 3.3雙速快速以太網(wǎng)收發(fā)器數(shù)據(jù)表
文件頁(yè)數(shù)： 13/70頁(yè)
文件大小： 833K
代理商： LXT972A
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
—
LXT972A
Datasheet
13
2.0
Signal Descriptions
Table 2. LXT972A MII Signal Descriptions
LQFP
Pin#
Symbol
Type
1
Signal Description
Data Interface Pins
60
59
58
57
TXD3
TXD2
TXD1
TXD0
I
Transmit Data
. TXD is a bundle of parallel data signals that are driven by the MAC.
TXD<3:0> shall transition synchronously with respect to the TX_CLK. TXD<0> is the least
significant bit.
56
TX_EN
I
Transmit Enable
. The MAC asserts this signal when it drives valid data on TXD. This
signal must be synchronized to TX_CLK.
55
TX_CLK
O
Transmit Clock
. TX_CLK is sourced by the PHY in both 10 and 100Mbps operations. 2.5
MHz for 10Mbps operation, 25 MHz for 100Mbps operation.
45
46
47
48
RXD3
RXD2
RXD1
RXD0
O
Receive Data
. RXD is a bundle of parallel signals that transition synchronously with
respect to the RX_CLK. RXD<0> is the least significant bit.
49
RX_DV
O
Receive Data Valid
. The LXT972A asserts this signal when it drives valid data on RXD.
This output is synchronous to RX_CLK.
53
RX_ER
O
Receive Error
. Signals a receive error condition has occurred. This output is synchronous
to RX_CLK.
54
TX_ER
I
Transmit Error
. Signals a transmit error condition. This signal must be synchronized to
TX_CLK.
52
RX_CLK
O
Receive Clock
. 25 MHz for 100Mbps operation, 2.5 MHz for 10Mbps operation. Refer to
“
Clock Requirements
”
on page 20
in the Functional Description section.
62
COL
O
Collision Detected
. The LXT972A asserts this output when a collision is detected. This
output remains High for the duration of the collision. This signal is asynchronous and is
inactive during full-duplex operation.
63
CRS
O
Carrier Sense
. During half-duplex operation (bit 0.8 = 0), the LXT972A asserts this output
when either transmitting or receiving data packets. During full-duplex operation (bit 0.8 = 1),
CRS is asserted during receive. CRS assertion is asynchronous with respect to RX_CLK.
CRS is de-asserted on loss of carrier, synchronous to RX_CLK.
MII Control Interface Pins
3
MDDIS
I
Management Disable
. When MDDIS is High, the MDIO is disabled from read and write
operations.
When MDDIS is Low at power up or reset, the Hardware Control Interface pins control only
the initial or
“
default
”
values of their respective register bits. After the power-up/reset cycle
is complete, bit control reverts to the MDIO serial channel.
43
MDC
I
Management Data Clock
. Clock for the MDIO serial data channel. Maximum frequency is
8 MHz.
42
MDIO
I/O
Management Data Input/Output
. Bidirectional serial data channel for PHY/STA
communication.
64
MDINT
OD
Management Data Interrupt
. When bit 18.1 = 1, an active Low output on this pin indicates
status change. Interrupt is cleared by reading Register 19.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
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LXT972ALC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
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