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| 型號： | LXT972A |
| 廠商： | Intel Corp. |
| 英文描述： | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| 中文描述： | 3.3雙速快速以太網(wǎng)收發(fā)器數(shù)據(jù)表 |
| 文件頁數(shù)： | 63/70頁 |
| 文件大?。?/td> | 833K |
| 代理商： | LXT972A |
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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
—
LXT972A
Datasheet
63
Table 43. Auto Negotiation Expansion (Address 6)
Bit
Name
Description
Type
1
Default
6.15:6
Reserved
Ignore on read.
RO
0
6.5
Base Page
This bit indicates the status of the Auto-Negotiation variable, base page. It
flags synchronization with the Auto-Negotiation state diagram allowing
detection of interrupted links. This bit is only used if bit 16.1 (Alternate NP
feature) is set.
1 = basepage = true
0 = basepage = false
RO/
LH
0
6.4
Parallel
Detection Fault
1 = Parallel detection fault has occurred.
0 = Parallel detection fault has not occurred.
RO/
LH
0
6.3
Link Partner
Next Page Able
1 = Link partner is next page able.
0 = Link partner is not next page able.
RO
0
6.2
Next Page Able
1 = Local device is next page able.
0 = Local device is not next page able.
RO
1
6.1
Page Received
1 = Indicates that a new page has been received and the received code
word has been loaded into register 5 (base pages) or register 8 (next
pages) as specified in clause 28 of 802.3. This bit is cleared on read. If bit
16.1 is set, the Page Received bit is also cleared when mr_page_rx = false
or transmit_disable = true.
RO
LH
0
6.0
Link Partner A/
N Able
1 = Link partner is auto-negotiation able.
0 = Link partner is not auto-negotiation able.
RO
0
1. RO = Read Only LH = Latching High
Table 44. Auto Negotiation Next Page Transmit Register (Address 7)
Bit
Name
Description
Type
1
Default
7.15
Next Page
(NP)
1 = Additional next pages follow
0 = Last page
R/W
0
7.14
Reserved
Write as 0, ignore on read
RO
0
7.13
Message Page
(MP)
1 = Message page
0 = Unformatted page
R/W
1
7.12
Acknowledge 2
(ACK2)
1 = Complies with message
0 = Can not comply with message
R/W
0
7.11
Toggle
(T)
1 = Previous value of the transmitted Link Code Word equalled logic
zero
0 = Previous value of the transmitted Link Code Word equalled logic
one
R/W
0
7.10:0
Message/
Unformatted Code
Field
R/W
00000000
001
1. RO = Read Only. R/W = Read/Write
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972M | Single-Port 10/100 Mbps PHY Transceiver |
| LXT9763 | Fast Ethernet 10/100 Hex Transceiver with Full MII |
| LXT9763HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
| LXT9784 | Transceiver Hardware Integrity Function Overview |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT972ALC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972LCHFB8 | 制造商:LEVEL_ONE 功能描述: |
| LXT972M | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| LXT973QC | 制造商:Intel 功能描述:LAN Transceiver, Dual, 100 Pin, Plastic, QFP |
| LXT974 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
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