參數(shù)資料
型號(hào)： LXT972A
廠商： Intel Corp.
英文描述： 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
中文描述： 3.3雙速快速以太網(wǎng)收發(fā)器數(shù)據(jù)表
文件頁(yè)數(shù)： 34/70頁(yè)
文件大?。?/td> 833K
代理商： LXT972A
LXT972A
—
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
34
Datasheet
3.7.3.2
PMA Sublayer
Link
In 100Mbps mode, the LXT972A establishes a link whenever the scrambler becomes locked and
remains locked for approximately 50ms. Whenever the scrambler loses lock (receiving less than 12
consecutive idle symbols during a 2ms window), the link are taken down. This provides a very
robust link, essentially filtering out any small noise hits that may otherwise disrupt the link.
Furthermore, 100M idle patterns will not bring up a 10M link.
The LXT972A reports link failure via the MII status bits (1.2 and 17.10) and interrupt functions. If
auto-negotiation is enabled, link failure causes the LXT972A to re-negotiate.
Link Failure Override
The LXT972A normally transmits data packets only if it detects the link is up. Setting bit 16.14 = 1
overrides this function, allowing the LXT972A to transmit data packets even when the link is
down. This feature is provided as a diagnostic tool. Note that auto-negotiation must be disabled to
transmit data packets in the absence of link. If auto-negotiation is enabled, the LXT972A
automatically transmits FLP bursts if the link is down.
Carrier Sense
For 100TX links, a start-of-stream delimiter (SSD) or /J/K symbol pair causes assertion of carrier
sense (CRS). An end-of-stream delimiter (ESD) or /T/R symbol pair causes de-assertion of CRS.
The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R; however, in this
case RX_ER is asserted for one clock cycle when CRS is de-asserted.
Usage of CRS for Interframe Gap (IFG) timing is
not
recommended for the following reasons:
De-assertion time for CRS is slightly longer than assertion time. This causes IFG intervals to
appear somewhat shorter to the MAC than it actually is on the wire.
CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half-
duplex mode.
Receive Data Valid
The LXT972A asserts RX_DV to indicate that the received data maps to valid symbols. However,
RXD outputs zeros until the received data is decoded and available for transfer to the controller.
3.7.3.3
Twisted-Pair PMD Sublayer
The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and
descrambling, line coding and decoding (MLT-3 for 100TX, Manchester for 10T), as well as
receiving, polarity correction, and baseline wander correction functions.
Scrambler/Descrambler
The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using
an 11-bit, data-independent polynomial. The receiver automatically decodes the polynomial
whenever IDLE symbols are received.
相關(guān)PDF資料
PDF描述
LXT972ALC 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
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LXT9763 Fast Ethernet 10/100 Hex Transceiver with Full MII
LXT9763HC LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC
LXT9784 Transceiver Hardware Integrity Function Overview
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LXT972ALC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
LXT972LCHFB8 制造商:LEVEL_ONE 功能描述:
LXT972M 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver
LXT973QC 制造商:Intel 功能描述:LAN Transceiver, Dual, 100 Pin, Plastic, QFP
LXT974 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers
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