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參數(shù)資料
| 型號(hào)： | LXT972A |
| 廠商： | Intel Corp. |
| 英文描述： | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| 中文描述： | 3.3雙速快速以太網(wǎng)收發(fā)器數(shù)據(jù)表 |
| 文件頁(yè)數(shù)： | 59/70頁(yè) |
| 文件大?。?/td> | 833K |
| 代理商： | LXT972A |
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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
—
LXT972A
Datasheet
59
1.12
10Mbps Full-Duplex
1 = PHY able to operate at 10Mbps in full-duplex mode
0 = PHY not able to operate at 10Mbps full-duplex mode
RO
1
1.11
10Mbps Half-Duplex
1 = PHY able to operate at 10Mbps in half-duplex mode
0 = PHY not able to operate at 10Mbps in half-duplex
RO
1
1.10
100BASE-T2 Full-
Duplex
Not Supported
1 = PHY able to perform full-duplex 100BASE-T2
0 = PHY not able to perform full-duplex 100BASE-T2
RO
0
1.9
100BASE-T2 Half-
Duplex
Not Supported
1 = PHY able to perform half duplex 100BASE-T2
0 = PHY not able to perform half-duplex 100BASE-T2
RO
0
1.8
Extended Status
1 = Extended status information in register 15
0 = No extended status information in register 15
RO
0
1.7
Reserved
1 = ignore when read
RO
0
1.6
MF Preamble
Suppression
1 = PHY accepts management frames with preamble suppressed
0 = PHY will not accept management frames with preamble
suppressed
RO
0
1.5
Auto-Negotiation
Complete
1 = Auto-negotiation complete
0 = Auto-negotiation not complete
RO
0
1.4
Remote Fault
1 = Remote fault condition detected
0 = No remote fault condition detected
RO/LH
0
1.3
Auto-Negotiation
Ability
1 = PHY is able to perform Auto-Negotiation
0 = PHY is not able to perform Auto-Negotiation
RO
1
1.2
Link Status
1 = Link is up
0 = Link is down
RO/LL
0
1.1
Jabber Detect
1 = Jabber condition detected
0 = Jabber condition not detected
RO/LH
0
1.0
Extended Capability
1 = Extended register capabilities
0 = Basic register capabilities
RO
1
Table 39. PHY Identification Register 1 (Address 2)
Bit
Name
Description
Type
1
Default
2.15:0
PHY ID
Number
The PHY identifier composed of bits 3 through 18 of the OUI.
RO
0013 hex
1. RO = Read Only
Table 38. MII Status Register #1 (Address 1)
Bit
Name
Description
Type
1
Default
1. RO = Read Only
LL = Latching Low
LH = Latching High
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972M | Single-Port 10/100 Mbps PHY Transceiver |
| LXT9763 | Fast Ethernet 10/100 Hex Transceiver with Full MII |
| LXT9763HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
| LXT9784 | Transceiver Hardware Integrity Function Overview |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT972ALC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972LCHFB8 | 制造商:LEVEL_ONE 功能描述: |
| LXT972M | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| LXT973QC | 制造商:Intel 功能描述:LAN Transceiver, Dual, 100 Pin, Plastic, QFP |
| LXT974 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
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