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參數(shù)資料
| 型號： | LXT972A |
| 廠商： | Intel Corp. |
| 英文描述： | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| 中文描述： | 3.3雙速快速以太網(wǎng)收發(fā)器數(shù)據(jù)表 |
| 文件頁數(shù)： | 64/70頁 |
| 文件大?。?/td> | 833K |
| 代理商： | LXT972A |
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LXT972A
—
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
64
Datasheet
Table 45. Auto Negotiation Link Partner Next Page Receive Register (Address 8)
Bit
Name
Description
Type
1
Default
8.15
Next Page
(NP)
1 = Link Partner has additional next pages to send
0 = Link Partner has no additional next pages to send
RO
0
8.14
Acknowledge
(ACK)
1 = Link Partner has received Link Code Word from LXT972A
0 = Link Partner has not received Link Code Word from LXT972A
RO
0
8.13
Message Page
(MP)
1 = Page sent by the Link Partner is a Message Page
0 = Page sent by the Link Partner is an Unformatted Page
RO
0
8.12
Acknowledge 2
(ACK2)
1 = Link Partner complies with the message
0 = Link Partner can not comply with the message
RO
0
8.11
Toggle
(T)
1 = Previous value of the transmitted Link Code Word equalled logic
zero
0 = Previous value of the transmitted Link Code Word equalled logic
one
RO
0
8.10:0
Message/
Unformatted Code
Field
User definable
RO
0
1. RO = Read Only.
Table 46. Configuration Register (Address 16, Hex 10)
Bit
Name
Description
Type
1
Default
16.15
Reserved
Write as zero, ignore on read.
R/W
0
16.14
Force Link Pass
1 = Force Link pass
0 = Normal operation
R/W
0
16.13
Transmit Disable
1 = Disable Twisted Pair transmitter
0 = Normal Operation
R/W
0
16.12
Bypass Scrambler
(100BASE-TX)
1 = Bypass Scrambler and Descrambler
0 = Normal Operation
R/W
0
16.11
Reserved
Ignore
R/W
0
16.10
Jabber
(10BASE-T)
1 = Disable Jabber Correction
0 = Normal operation
R/W
0
16.9
SQE
(10BASE-T)
1 = Enable Heart Beat
0 = Disable Heart Beat
R/W
0
16.8
TP Loopback
(10BASE-T)
1 = Disable TP loopback during half-duplex operation
0 = Normal Operation
R/W
0
16.7
CRS Select
(10BASE-T)
1 = CRS deassert extends to RX_DV deassert
0 = Normal Operation
R/W
1
16.6
Reserved
Write as zero, ignore on read.
R/W
0
16.5
PRE_EN
Preamble Enable.
0 = Set RX_DV high coincident with SFD.
1 = Set RX_DV high and RXD = preamble when CRS is asserted.
R/W
0
16.4:3
Reserved
Write as zero, ignore on read.
R/W
00
1. R/W = Read /Write, LHR = Latches High on Reset
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|---|---|
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| LXT9763 | Fast Ethernet 10/100 Hex Transceiver with Full MII |
| LXT9763HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LXT972ALC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972LCHFB8 | 制造商:LEVEL_ONE 功能描述: |
| LXT972M | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| LXT973QC | 制造商:Intel 功能描述:LAN Transceiver, Dual, 100 Pin, Plastic, QFP |
| LXT974 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
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