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參數(shù)資料
| 型號(hào)： | LXT972A |
| 廠商： | Intel Corp. |
| 英文描述： | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| 中文描述： | 3.3雙速快速以太網(wǎng)收發(fā)器數(shù)據(jù)表 |
| 文件頁(yè)數(shù)： | 24/70頁(yè) |
| 文件大?。?/td> | 833K |
| 代理商： | LXT972A |
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LXT972A
—
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
24
Datasheet
3.5
Establishing Link
See
Figure 8
for an overview of link establishment.
3.5.1
Auto-Negotiation
If not configured for forced operation, the LXT972A attempts to auto-negotiate with its link
partner by sending Fast Link Pulse (FLP) bursts. Each burst consists of up to 33 link pulses spaced
62.5
μ
s apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may
be present or absent to indicate a
“
1
”
or a
“
0
”
. Each FLP burst exchanges 16 bits of data, which are
referred to as a
“
link code word
”
. All devices that support auto-negotiation must implement the
“
Base Page
”
defined by IEEE 802.3 (registers 4 and 5). LXT972A also supports the optional
“
Next
Page
”
function as described in
Table 44
and
Table 45
(registers 7 and 8).
3.5.1.1
Base Page Exchange
By exchanging Base Pages, the LXT972A and its link partner communicate their capabilities to
each other. Both sides must receive at least three identical base pages for negotiation to continue.
Each side identifies the highest common capabilities that both sides support and configures itself
accordingly.
3.5.1.2
Next Page Exchange
Additional information, above that required by base page exchange, is also sent via
“
Next Pages
’
.
The LXT972A fully supports the IEEE 802.3ab method of negotiation via Next Page exchange.
Table 8. Hardware Configuration Settings
Desired Mode
LED/CFG
n
Pin Settings
1
Resulting Register Bit Values
Control Register
Auto-Neg Advertisement
Auto-Neg
Speed
(Mbps)
Duplex
1
2
3
AutoNeg
0.12
Speed
0.13
FD
0.8
100FD
4.8
100TX
4.7
10FD
4.6
10T
4.5
Disabled
10
Half
Low
Low
Low
0
0
0
N/A
Auto-Negotiation Advertisement
Full
Low
Low
High
1
100
Half
Low
High
Low
1
0
Full
Low
High
High
1
Enabled
100 Only
Half
High
Low
Low
1
1
0
0
1
0
0
Full
High
Low
High
1
1
1
0
0
10/100
Half Only
High
High
Low
0
0
1
0
1
Full or
Half
High
High
High
1
1
1
1
1
1. Refer to
Table 7 on page 15
for LED/CFG pin assignments.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972M | Single-Port 10/100 Mbps PHY Transceiver |
| LXT9763 | Fast Ethernet 10/100 Hex Transceiver with Full MII |
| LXT9763HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
| LXT9784 | Transceiver Hardware Integrity Function Overview |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT972ALC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972LCHFB8 | 制造商:LEVEL_ONE 功能描述: |
| LXT972M | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| LXT973QC | 制造商:Intel 功能描述:LAN Transceiver, Dual, 100 Pin, Plastic, QFP |
| LXT974 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
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