參數(shù)資料
型號(hào): LXT972A
廠商: Intel Corp.
英文描述: 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
中文描述: 3.3雙速快速以太網(wǎng)收發(fā)器數(shù)據(jù)表
文件頁(yè)數(shù): 58/70頁(yè)
文件大?。?/td> 833K
代理商: LXT972A
LXT972A
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
58
Datasheet
Table 37. Control Register (Address 0)
Bit
Name
Description
Type
1
Default
0.15
Reset
1 = PHY reset
0 = Normal operation
R/W
SC
0
0.14
Loopback
1 = Enable loopback mode
0 = Disable loopback mode
R/W
0
0.13
Speed Selection
0.6
0.13
Speed Selected
R/W
Note 2
1
1
0
0
1
0
1
0
Reserved
1000Mbps (not supported)
100Mbps
10Mbps
0.12
Auto-Negotiation
Enable
1 = Enable Auto-Negotiation Process
0 = Disable Auto-Negotiation Process
R/W
Note 2
0.11
Power-Down
1 = Power-down
0 = Normal operation
R/W
0
0.10
Isolate
1 = Electrically isolate PHY from MII
0 = Normal operation
R/W
0
0.9
Restart
Auto-Negotiation
1 = Restart Auto-Negotiation Process
0 = Normal operation
R/W
SC
0
0.8
Duplex Mode
1 = Full Duplex
0 = Half Duplex
R/W
Note 2
0.7
Collision Test
1 = Enable COL signal test
0 = Disable COL signal test
R/W
0
0.6
Speed Selection
0.6
0.13
Speed Selected
R/W
0
1
1
0
0
1
0
1
0
Reserved
1000Mbps (not supported)
100Mbps
10Mbps
0.5:0
Reserved
Write as 0, ignore on Read
R/W
00000
1. R/W = Read/Write
RO = Read Only
SC = Self Clearing
2. Default value of bits 0.12, 0.13 and 0.8 are determined by the LED/CFG pins (refer to
Table 8 on page 24
).
Table 38. MII Status Register #1 (Address 1)
Bit
Name
Description
Type
1
Default
1.15
100BASE-T4
Not Supported
1 = PHY able to perform 100BASE-T4
0 = PHY not able to perform 100BASE-T4
RO
0
1.14
100BASE-X Full-
Duplex
1 = PHY able to perform full-duplex 100BASE-X
0 = PHY not able to perform full-duplex 100BASE-X
RO
1
1.13
100BASE-X Half-
Duplex
1 = PHY able to perform half-duplex 100BASE-X
0 = PHY not able to perform half-duplex 100BASE-X
RO
1
1. RO = Read Only
LL = Latching Low
LH = Latching High
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