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參數(shù)資料
| 型號： | LXT972A |
| 廠商： | Intel Corp. |
| 英文描述： | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| 中文描述： | 3.3雙速快速以太網(wǎng)收發(fā)器數(shù)據(jù)表 |
| 文件頁數(shù)： | 35/70頁 |
| 文件大?。?/td> | 833K |
| 代理商： | LXT972A |
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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
—
LXT972A
Datasheet
35
Scrambler Seeding.
Once the transmit data (or Idle symbols) are properly encoded, they are
scrambled to further reduce EMI and to spread the power spectrum using an 11-bit scrambler seed.
Five seed bits are determined by the PHY address, and the remaining bits are hard coded in the
design.
Scrambler Bypass.
The scrambler/descrambler can be bypassed by setting bit 16.12 = 1.
Scrambler bypass is provided for diagnostic and test support.
Baseline Wander Correction
The LXT972A provides a baseline wander correction function which makes the device robust
under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is by
definition
“
unbalanced
”
. This means that the average value of the signal voltage can
“
wander
”
significantly over short time intervals (tenths of seconds). This wander can cause receiver errors at
long-line lengths (100 meters) in less robust designs. Exact characteristics of the wander are
completely data dependent.
The LXT972A baseline wander correction characteristics allow the device to recover error-free
data while receiving worst-case
“
killer
”
packets over all cable lengths.
Polarity Correction
The 100BASE-TX descrambler automatically detects and corrects for the condition where the
receive signal at TPIP and TPIN is inverted.
Programmable Slew Rate Control
The LXT972A device supports a slew rate mechanism whereby one of four pre-selected slew rates
can be used. This allows the designer to optimize the output waveform to match the characteristics
of the magnetics. The slew rate is determined by the TxSLEW pins as shown in
Table 4 on page 14
.
3.8
10Mbps Operation
The LXT972A operates as a standard 10BASE-T transceiver. The LXT972A supports all the
standard 10Mbps functions. During 10BASE-T (10T) operation, the LXT972A transmits and
receives Manchester-encoded data across the network link. When the MAC is not actively
transmitting data, the LXT972A drives link pulses onto the line.
In 10T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded signals
received from the network are decoded by the LXT972A and sent across the MII to the MAC.
3.8.1
10T Preamble Handling
The LXT972A offers two options for preamble handling, selected by bit 16.5. In 10T Mode when
16.5 = 0, the LXT972A strips the entire preamble off of received packets. CRS is asserted
coincident with SFD. RX_DV is held Low for the duration of the preamble. When RX_DV is
asserted, the very first two nibbles driven by the LXT972A are the SFD
“
5D
”
hex followed by the
body of the packet.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972M | Single-Port 10/100 Mbps PHY Transceiver |
| LXT9763 | Fast Ethernet 10/100 Hex Transceiver with Full MII |
| LXT9763HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
| LXT9784 | Transceiver Hardware Integrity Function Overview |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT972ALC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972LCHFB8 | 制造商:LEVEL_ONE 功能描述: |
| LXT972M | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| LXT973QC | 制造商:Intel 功能描述:LAN Transceiver, Dual, 100 Pin, Plastic, QFP |
| LXT974 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
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