參數(shù)資料
型號: LXT972A
廠商: Intel Corp.
英文描述: 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
中文描述: 3.3雙速快速以太網(wǎng)收發(fā)器數(shù)據(jù)表
文件頁數(shù): 31/70頁
文件大小: 833K
代理商: LXT972A
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
LXT972A
Datasheet
31
3.7.2
Collision Indication
Figure 17
shows normal transmission. Upon detection of a collision, the COL output is asserted
and remains asserted for the duration of the collision as shown in
Figure 18
.
3.7.3
100BASE-X Protocol Sublayer Operations
With respect to the 7-layer communications model, the LXT972A is a Physical Layer 1 (PHY)
device. The LXT972A implements the Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model
defined by the IEEE 802.3u standard. The following paragraphs discuss LXT972A operation from
the reference model point of view.
3.7.3.1
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/
decoding function.
For 100TX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long
as TX_EN is de-asserted.
Figure 17. 100BASE-TX Transmission with no Errors
Figure 18. 100BASE-TX Transmission with Collision
DA
DA DA
DA
DA
DA
DA
DA
DA
TX_CLK
TX_EN
TXD<3:0>
CRS
COL
P
R
E
A
M
B
L
E
JAM
TX_CLK
TX_EN
TXD<3:0>
CRS
COL
P
R
E
A
M
B
L
E
JAM
JAM
JAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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