參數(shù)資料
型號(hào): LXT972A
廠商: Intel Corp.
英文描述: 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
中文描述: 3.3雙速快速以太網(wǎng)收發(fā)器數(shù)據(jù)表
文件頁(yè)數(shù): 47/70頁(yè)
文件大?。?/td> 833K
代理商: LXT972A
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
LXT972A
Datasheet
47
5.2
Timing Diagrams
Figure 24. 100BASE-TX Receive Timing - 4B Mode
Table 25. 100BASE-TX Receive Timing Parameters - 4B Mode
Parameter
Sym
Min
Typ
1
Max
Units
2
Test Conditions
RXD<3:0>, RX_DV, RX_ER setup
to RX_CLK High
t1
10
ns
RXD<3:0>, RX_DV, RX_ER hold
from RX_CLK High
t2
10
ns
CRS asserted to RXD<3:0>, RX_DV
t3
3
5
BT
Receive start of
J
to CRS asserted
t4
12
16
BT
Receive start of
T
to CRS de-asserted
t5
10
17
BT
Receive start of
J
to COL asserted
t6
16
22
BT
Receive start of
T
to COL de-asserted
t7
17
20
BT
1. Typical values are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10
-
s or 10 ns.
t4
t5
t3
t6
t7
0ns
250ns
CRS
RX_DV
RXD<3:0>
RX_CLK
COL
t1
t2
TPI
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