參數(shù)資料
型號(hào): LXT972A
廠商: Intel Corp.
英文描述: 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
中文描述: 3.3雙速快速以太網(wǎng)收發(fā)器數(shù)據(jù)表
文件頁(yè)數(shù): 61/70頁(yè)
文件大?。?/td> 833K
代理商: LXT972A
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
LXT972A
Datasheet
61
Table 41. Auto Negotiation Advertisement Register (Address 4)
Bit
Name
Description
Type
1
Default
4.15
Next Page
1 = Port has ability to send multiple pages.
0 = Port has no ability to send multiple pages.
R/W
0
4.14
Reserved
Ignore.
RO
0
4.13
Remote Fault
1 = Remote fault.
0 = No remote fault.
R/W
0
4.12
Reserved
Ignore.
R/W
0
4.11
Asymmetric
Pause
Pause operation defined in Clause 40 and 27.
R/W
0
4.10
Pause
1 = Pause operation enabled for full-duplex links.
0 = Pause operation disabled.
R/W
Note 2
4.9
100BASE-T4
1 = 100BASE-T4 capability is available.
0 = 100BASE-T4 capability is not available.
(The LXT972A does not support 100BASE-T4 but allows this bit to be set to
advertise in the Auto-Negotiation sequence for 100BASE-T4 operation. An
external 100BASE-T4 transceiver could be switched in if this capability is
desired.)
R/W
0
4.8
100BASE-TX
full-duplex
1 = Port is 100BASE-TX full-duplex capable.
0 = Port is not 100BASE-TX full-duplex capable.
R/W
Note 3
4.7
100BASE-TX
1 = Port is 100BASE-TX capable.
0 = Port is not 100BASE-TX capable.
R/W
Note 3
4.6
10BASE-T
full-duplex
1 = Port is 10BASE-T full-duplex capable.
0 = Port is not 10BASE-T full-duplex capable.
R/W
Note 3
4.5
10BASE-T
1 = Port is 10BASE-T capable.
0 = Port is not 10BASE-T capable.
R/W
Note 3
4.4:0
Selector Field,
S<4:0>
<00001> = IEEE 802.3.
<00010> = IEEE 802.9 ISLAN-16T.
<00000> = Reserved for future Auto-Negotiation development.
<11111> = Reserved for future Auto-Negotiation development.
Unspecified or reserved combinations should not be transmitted.
R/W
00001
1. R/W = Read/Write
RO = Read Only
2. Default value of bit 4.10 is determined by pin 33/H8.
3. Default values of bits 4.5, 4.6, 4.7, and 4.8 are determined by LED/CFG
n
pins at reset. Refer to
Table 8
for details.
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