- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377799 > LXT972A (Intel Corp.) 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet PDF資料下載
參數(shù)資料
| 型號(hào)： | LXT972A |
| 廠商： | Intel Corp. |
| 英文描述： | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| 中文描述： | 3.3雙速快速以太網(wǎng)收發(fā)器數(shù)據(jù)表 |
| 文件頁(yè)數(shù)： | 65/70頁(yè) |
| 文件大?。?/td> | 833K |
| 代理商： | LXT972A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)當(dāng)前第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
—
LXT972A
Datasheet
65
16.2
Reserved
Write as zero, ignore on read.
R/W
0
16.1
Alternate NP
feature
1 = Enable alternate auto negotiate next page feature.
0 = Disable alternate auto negotiate next page feature
R/W
0
16.0
Reserved
Write as zero, ignore on read.
R/W
0
Table 47. Status Register #2 (Address 17)
Bit
Name
Description
Type
1
Default
17.15
Reserved
Always 0.
RO
0
17.14
10/100 Mode
1 = LXT972A is operating in 100BASE-TX mode.
0 = LXT972A is not operating 100BASE-TX mode.
RO
0
17.13
Transmit Status
1 = LXT972A is transmitting a packet.
0 = LXT972A is not transmitting a packet.
RO
0
17.12
Receive Status
1 = LXT972A is receiving a packet.
0 = LXT972A is not receiving a packet.
RO
0
17.11
Collision Status
1 = Collision is occurring.
0 = No collision.
RO
0
17.10
Link
1 = Link is up.
0 = Link is down.
RO
0
17.9
Duplex Mode
1 = Full-duplex.
0 = Half-duplex.
RO
0
17.8
Auto-Negotiation
1 = LXT972A is in Auto-Negotiation Mode.
0 = LXT972A is in manual mode.
RO
0
17.7
Auto-Negotiation
Complete
1 = Auto-negotiation process completed.
0 = Auto-negotiation process not completed.
This bit is only valid when auto negotiate is enabled, and is equivalent
to bit 1.5.
RO
0
17.6
Reserved
Reserved.
RO
0
17.5
Polarity
1 = Polarity is reversed.
0 = Polarity is not reversed.
RO
0
17.4
Pause
1 = Device Pause capable.
0 = Device Not Pause capable.
RO
0
17:3
Error
1 = Error Occurred (Remote Fault, X,Y,Z).
0 = No error occurred.
RO
0
17:2
Reserved
Always 0.
RO
0
17:1
Reserved
Always 0.
RO
0
17.0
Reserved
Always 0.
RO
0
1. RO = Read Only. R/W = Read/Write
Table 46. Configuration Register (Address 16, Hex 10) (Continued)
Bit
Name
Description
Type
1
Default
1. R/W = Read /Write, LHR = Latches High on Reset
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972M | Single-Port 10/100 Mbps PHY Transceiver |
| LXT9763 | Fast Ethernet 10/100 Hex Transceiver with Full MII |
| LXT9763HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
| LXT9784 | Transceiver Hardware Integrity Function Overview |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT972ALC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972LCHFB8 | 制造商:LEVEL_ONE 功能描述: |
| LXT972M | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| LXT973QC | 制造商:Intel 功能描述:LAN Transceiver, Dual, 100 Pin, Plastic, QFP |
| LXT974 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。