參數(shù)資料
型號(hào)： LXT972A
廠商： Intel Corp.
英文描述： 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
中文描述： 3.3雙速快速以太網(wǎng)收發(fā)器數(shù)據(jù)表
文件頁(yè)數(shù)： 18/70頁(yè)
文件大小： 833K
代理商： LXT972A
LXT972A
—
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
18
Datasheet
When the LXT972A receives a Remote Fault indication from its partner during auto-negotiation it:
sets bit 5.13 in the Link Partner Base Page Ability Register, and
sets the Remote Fault bit 1.4 in the MII Status Register to pass this information to the local
controller.
3.2.2
MII Data Interface
The LXT972A supports a standard Media Independent Interface (MII). The MII consists of a data
interface and a management interface. The MII Data Interface passes data between the LXT972A
and a Media Access Controller (MAC). Separate parallel buses are provided for transmit and
receive. This interface operates at either 10Mbps or 100Mbps. The speed is set automatically, once
the operating conditions of the network link have been determined. Refer to
“
MII Operation
”
on
page 25
for additional details.
3.2.3
Configuration Management Interface
The LXT972A provides both an MDIO interface and a Hardware Control Interface for device
configuration and management.
3.2.3.1
MDIO Management Interface
The LXT972A supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to
monitor and control the state of the LXT972A. The MDIO interface consists of a physical
connection, a specific protocol that runs across the connection, and an internal set of addressable
registers.
Some registers are required and their functions are defined by the IEEE 802.3 standard. The
LXT972A also supports additional registers for expanded functionality. The LXT972A supports
multiple internal registers, each of which is 16 bits wide. Specific register bits are referenced using
an
“
X.Y
”
notation, where X is the register number (0-31) and Y is the bit number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this
interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read and write
operations are disabled and the Hardware Control Interface provides primary configuration control.
When MDDIS is Low, the MDIO port is enabled for both read and write operations and the
Hardware Control Interface is not used.
MDIO Addressing
The protocol allows one controller to communicate between two LXT972A chips. Pin ADDR0 is
set high or low to determine the chip address.
相關(guān)PDF資料
PDF描述
LXT972ALC 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
LXT972M Single-Port 10/100 Mbps PHY Transceiver
LXT9763 Fast Ethernet 10/100 Hex Transceiver with Full MII
LXT9763HC LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC
LXT9784 Transceiver Hardware Integrity Function Overview
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LXT972ALC 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
LXT972LCHFB8 制造商:LEVEL_ONE 功能描述:
LXT972M 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver
LXT973QC 制造商:Intel 功能描述:LAN Transceiver, Dual, 100 Pin, Plastic, QFP
LXT974 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers
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