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參數(shù)資料
| 型號(hào)： | MC68322FT16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.667 MHz, RISC PROCESSOR, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 14/283頁(yè) |
| 文件大小： | 1602K |
| 代理商： | MC68322FT16 |
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Parallel Port Interface
MOTOROLA
MC68322 USER’S MANUAL
9-11
9.3 SOFTWARE-CONTROLLED HANDSHAKING
By clearing the PPCR’s MODE field, the software controls all parallel port operations,
including negotiation and termination phases, as well as reverse data transfers. The
software can also respond to parallel port inputs by way of polling or interrupts. This gives
the software the flexibility to adapt to new and revised protocols. The software controls
BUSY and ACK with the BSY2 and ACK2 bits in the PPIR. Normally, the PPI state machine
should be idle when using BSY2 and ACK2. The software can issue a reset (by setting the
RST bit in the PPCR) to force the PPI state machine to idle.
When polling, status bits in the PIER report the logic level at each parallel port input pin and
control bits allow separate and direct control of each of the output pins. The host inputs are
always synchronized to the internally generated CLK1 signal to prevent metastable events
from reaching the microprocessor. This results in a maximum of one CLK1 period of delay
before an external event appears in the PIER. The SELECTIN, INIT, AUTOFD, and
STROBE signals can also be digitally filtered to improve noise immunity. Digital filtering
adds another CLK1 period of delay before level changes on these signals are indicated in
the PIER.
9.4 DIGITAL FILTERING
The MC68322 contains digital filter circuitry on host control signal inputs (SELECTIN,
STROBE, AUTOFD, and INIT) to improve noise immunity and make the PPI more
impervious to inductive switching noise. Digital filtering can be enabled, regardless of
whether hardware handshaking is enabled or disabled. When digital filtering is disabled, the
host control signals are synchronized to the internally generated CLK1 signal to prevent
metastable events from reaching the internal logic of the MC68322. However, the
synchronization logic does not prevent glitches on the host control signals from reaching the
PPI’s internal logic and causing spurious events.
When digital filtering is enabled, the host control signals are first synchronized and then
passed through individual digital filters. The digital filter samples the host input on the rising
edge of CLK1 and passes a logic level change through, but only if the host signal is sampled
at the same logic level for a second consecutive clock. Digital filtering protects internal logic
from glitches as wide as one CLK1 period. Such internal logic includes the hardware
handshake control logic, the PPCR, and the parallel port interrupt controller.
Synchronization plus digital filtering adds two CLK1 periods of delay before a level change
on one of the host signals appears in the PPCR, and three CLK1 periods of delay before an
output responds to an input (before BUSY responds to STROBE). Likewise, synchronization
and digital filtering of STROBE affect the point at which PD7–PD0 and AUTOFD are latched
into the PPIR. Without digital filtering, PD7–PD0 and AUTOFD are sampled on the second
rising edge of CLK1 after STROBE is first sampled low. With digital filtering, PD7–PD0 and
AUTOFD are sampled on the third rising edge of CLK1 after STROBE is first sampled low.
Digital filtering can be disabled to avoid the one clock penalty that it adds to recognizing
input signals. This is an option in specialized applications that have a high bandwidth
requirement and the ability to guarantee signal integrity between the host and the printer.
Otherwise, it is highly recommended that digital filtering be enabled.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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