Graphic Operations
MOTOROLA
MC68322 USER’S MANUAL
12-15
12.9 LOCATION AND ADDRESS CONSTRAINTS
Display lists, scanline tables, and halftone tables must reside in DRAM space because the
graphics unit cannot access chip-select space. The graphics unit can, however, fetch
instructions from any of the MC68322’s six DRAM channels and from one channel to
another if two channels define a continuous region of memory. Keep in mind though, that
due to its internal prefetch queues, the graphics unit must be able to read eight words
beyond every display list, scanline table, and halftone table. If this rule is broken, an RGP
error interrupt event could occur and cause the graphics unit to shut down.
The addressing conventions discussed in previous sections also apply to graphic order
address parameters. All address fields are 32 bits wide. Address parameters that reference
bit maps specify bit addresses, while all others require conventional byte addresses. The
RGP requires all display lists, scanline tables, and companion halftone tables to start on
word-aligned addresses. Since all graphic orders, bit string specifiers, and halftone
specifiers are an even number of bytes in length, this guarantees that all successive orders
and specifiers begin at word-aligned addresses as well. This requirement also guarantees
that all word and long-word operands and field values are aligned on word boundaries. This
is important for the core, which can access word and long-word data only on word
boundaries. These rules do not apply to the actual bitmap data, which has no alignment
requirements.
The RGP internally stores all addresses in 32-bit registers and performs all address
calculations using 32-bit arithmetic. When the RGP makes an access to DRAM for bitmap
data, the bitmap address must first be converted to a byte address to accommodate the
fetch. This conversion is done first by stripping off the low order four bits (these bits select a
bit within the word) and then shifting the address to the right by three bits. This produces a
word-aligned byte address that is used for a 16-bit DRAM fetch of the bitmap data.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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