xiv
MC68322 USER’S MANUAL
MOTOROLA
LIST OF ILLUSTRATIONS
Figure
Page
Number
Title
Number
1-1.
MC68322 Block Diagram .................................................................................1-3
1-2.
Graphics Unit Data Flow Diagram ....................................................................1-5
1-3.
16M Memory Map ............................................................................................1-7
1-4.
256M Memory Map ..........................................................................................1-7
1-5.
Memory Map Address Register ........................................................................1-7
1-6.
Bitmap Structure ..............................................................................................1-9
1-7.
Unpacked And Packed Bitmaps .......................................................................1-9
1-8.
Duplex Laser Printer Paper Path ...................................................................1-11
1-9.
Example of a Duplex Printing Operation ........................................................1-12
2-1.
Functional Signal Groups .................................................................................2-1
2-2.
CLK1 Phase Relationship ................................................................................2-4
3-1.
EC000 Core Programming Model ....................................................................3-2
4-1.
Read Cycle Flowchart ......................................................................................4-2
4-2.
External Timing Diagram to Chip-Selects Banks .............................................4-2
4-3.
External Timing Diagram to Chip-Select Banks ...............................................4-3
4-4.
Word and Byte Read Cycle Timing Diagram to DRAM ....................................4-3
4-5.
Write Cycle Flowchart ......................................................................................4-4
4-6.
Word and Byte Write Cycle Timing Diagram to Chip-Selects ..........................4-5
4-7.
Word Write Cycle Timing Diagram to DRAM ...................................................4-6
4-8.
Internal Interrupt Acknowledge Cycle ..............................................................4-7
4-9.
Interrupt Acknowledge Cycle Timing Diagram .................................................4-7
4-10.
Reset Operation Timing Diagram .....................................................................4-8
4-11.
Bus Arbitration Timing Diagram .....................................................................4-10
4-12.
External Bus Master Read Cycle ...................................................................4-11
4-13.
External Bus Master Write Cycle ...................................................................4-12
5-1.
Software Interrupt Event Register ....................................................................5-3
5-2.
External Interrupt Registers (EXIR0/2–EXIR1/3) .............................................5-4
5-3.
Timer Register ..................................................................................................5-6
5-4.
Timer Interrupt Event Register .........................................................................5-6
5-5.
General Exception Processing Flowchart ........................................................5-7
5-6.
General Form of an Exception Stack Frame ....................................................5-8
5-7.
Module Soft-Reset Register ...........................................................................5-14
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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