DMA Interface
8-6
MC68322 USER’S MANUAL
MOTOROLA
ILA—Illegal Address
An illegal address interrupt is generated if a DMA channel attempts to access a DRAM or
chip-select bank using an out-of-range address. This bit is set if the channel’s configuration
register GDTA, GCSTA, or PDTA fields do not access a valid address. If this error occurs,
the DMA channel will halt all transfer operations and park in an error condition. The DMA
channel must then be reset using the soft-reset register’s GDR or PDR bits before starting
a new operation.
The interrupt level field indicates the interrupt level. If any of the events in the channel’s
interrupt event register occur, an interrupt level indicated by this field is sent to the EC000
core. The interrupt levels range from seven to zero (zero disables interrupts).
8.5 INITIATING A DMA OPERATION
The DMA channel is activated after programming the channel’s configuration register and
writing the transfer count field. The software must ensure that a DMA channel is idle before
writing the transfer count field. Writing a zero value to the transfer count field is allowed, but
not recommended. New values should not be written into the DMA registers during active
transfers because undefined results will occur.
For transfers to the MC68322 bus from DRAM, the GDMA immediately requests data from
DRAM. After receiving data from DRAM, the GDMA begins monitoring the external DREQ
input. When the external DMA device requests data, it is read out of the internal data latch
and presented through the MC68322 bus to complete the data transfer. This process
continues until all data is transferred, an address error occurs, or the transfer is terminated
by the core through a flush request.
For data transfers to DRAM from the MC68322 bus, the GDMA begins monitoring the
external DREQ input. When data is available from the external DMA device, the MC68322
bus cycle starts and the data is loaded into the internal data latch. Once the internal data
latch is loaded with source data, the GDMA requests a DRAM cycle and, when granted,
writes the data to memory. This process continues until all data is transferred, an address
error occurs, or the transfer is terminated by the core through a flush request.
During an active DMA transfer, the system software can decide to reallocate the DMA
resource to another device. By issuing a flush request, the current DMA operation will be
terminated. When the CMP bit in the interrupt event register is set, new values for the DMA
channel registers can be written and the channel restarted.
8.6 DMA TRANSFERS
Because both DMA channels operate on a demand basis, all DMA-initiated transfers
(through either the PDMA or GDMA channels) use a data request and acknowledge type
handshake.
The GDMA supports both word- and byte-sized transfers. For word-sized transfers, the
external DMA device must connect to D15–D0 and for byte-sized transfers the device must
connect to D7–D0. WRU and WRL signals are both asserted during an MC68322
word-sized bus write cycle, but only WRL is asserted during byte-sized writes.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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