Index
Index-2
MC68322 USER’S MANUAL
MOTOROLA
BLT2BB_D, 13-9
BLT2BB_SD, 13-11
BLT2BB_SHD, 13-13
BLT2BB_XD, 13-17
BLT2BB_XHD, 13-22
BLT2F_D, 13-27
BLT2F_SD, 13-28
BLT2F_SHD, 13-29
BLT2F_XD, 13-31
BLT2F_XHD, 13-33
BLT2UB_D, 13-36
BLT2UB_SD, 13-37
BLT2UB_SHD, 13-38
BLT2UB_XD, 13-40
BLT2UB_XHD, 13-43
Boolean
code calculating example 12-4
specifying a graphic operatin transfer, 12-3
Boolean codes, 12-3
Boolean logic unit, 11-1
bottom-to-top (B2T), definition, 13-6
BR, asserting, 4-10
burst accesses, DRAM, 7-10
burst cycles
DRAM access 7-1
bus 4-1
address, 2-3
data, 2-3
bus arbitration
DRAM, 7-9
signals, asserting, 4-9
bus arbitration, 4-9
bus cycle, exception, 5-13
bus cycles
DRAM read cycles 7-7
DRAM write cycles 7-8
bus interface unit
GDMA read cycles, performing 8-7
bus mastership, exchanging, 4-9
bus operation
core read cycle, 4-1
core write cycle, 4-4
external bus master, 4-9
interrupt acknowledge bus cycle, 4-6
reset, 4-8
bus operation, 4-1
BUZZER ENB, D-3
BUZZER INT, D-3
byte address, defined 13-5
byte operation, 4-1, 4-4
C
CCLK supplied by MC68322, 10-11, 10-13
CCLK supplied by print engine, 10-12, 10-14
channel address
command received interrupt 9-7
chip-select
recovery value, 6-4
chip-select DMA timing register, 6-3
chip-selects
active read and write times 6-2
banks
DMA access timing, 8-8
location priority 6-3
banks, chip-select registers 6-1
data transfers
synchronous timing values, 6-4
minimum value timings, 6-2
registers
chip-select DMA timing register 6-3
chip-select recovery, 6-4
DMA access timing 8-8
location, 6-3
registers at reset, 6-3
size encodings, 6-2
timing characteristics, 6-2
clipping expanded bit maps 13-3
clocks
command, supplying 10-2
status, supplying, 10-2
video, divisor operation, 10-15
command byte detection, 9-9
command bytes
during ECP mode 9-3
commands to the print engine, 10-11
communications modes, 9-1
compatibility mode (see handshaking)
core
data types and addressing modes, 3-3
DRAM write cycle, 7-9
DRAMcontroller
accesses and refresh cycle, 7-6
instruction set summary, 3-4, 3-6
notational conventions, 3-4
programming model, 3-1
core read cycle, 4-1
core write cycle, 4-4
core, 3-1
CSDTR, 6-3
CSR, 6-1
CSR, (see chip-selects, registers)
CSRR, 6-4
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Freescale Semiconductor, Inc.
For More Information On This Product,
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