TABLE OF CONTENTS (Continued)
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Title
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MOTOROLA
MC68322 USER’S MANUAL
ix
Section 7
DRAM Controller
7.1
DRAM Registers and Banks .................................................................7-1
7.1.1
Base Address and Size Fields ...................................................7-1
7.1.2
ROM Mode .................................................................................7-2
7.1.2.1
Functional Description ....................................................7-2
7.1.2.2
Timing Example ..............................................................7-3
7.1.2.3
Address Demultiplexing Circuit .......................................7-4
7.1.2.4
Operational Example ......................................................7-4
7.2
DRAM Control Register ........................................................................7-5
7.3
DRAM Timing Modes ...........................................................................7-5
7.4
DRAM Accesses ..................................................................................7-6
7.4.1
DRAM Refresh Cycles ...............................................................7-6
7.4.2
DRAM Read Cycles ...................................................................7-7
7.4.3
DRAM Write Cycles ....................................................................7-8
7.4.4
DRAM Bus Arbitration ................................................................7-9
7.4.5
DRAM Burst Accesses .............................................................7-10
7.5
Power-Up Sequence ..........................................................................7-10
Section 8
DMA Interface
8.1
DMA Configuration Registers ...............................................................8-2
8.1.1
Transfer Address Fields .............................................................8-2
8.1.2
Transfer Count Fields .................................................................8-3
8.1.3
Flush Request Fields ..................................................................8-3
8.2
GDMA Control Register ........................................................................8-3
8.3
DMA Speed Register ............................................................................8-4
8.4
DMA Interrupt Event Registers .............................................................8-5
8.5
Initiating A DMA Operation ...................................................................8-6
8.6
DMA Transfers .....................................................................................8-6
8.6.1
PDMA Transfers .........................................................................8-7
8.6.2
GDMA MC68322 Bus Read and Write Cycles ...........................8-7
8.6.3
GDMA DRAM Bus Read and Write Cycles ................................8-8
8.7
DMA Transfer Termination ...................................................................8-9
8.7.1
Normal Termination ....................................................................8-9
8.7.2
Bad Address Termination .........................................................8-10
8.7.3
Core-Forced Termination .........................................................8-10
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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