LIST OF ILLUSTRATIONS (Continued)
Figure
Page
Number
Title
Number
MOTOROLA
MC68322 USER’S MANUAL
xv
6-1.
Chip-Select Register (CSR7–CSR0) ................................................................6-1
6-2.
Chip-Select DMA Timing and Recovery Registers ..........................................6-3
6-3.
Synchronous Read or Write Timing Diagram ...................................................6-5
6-4.
Asynchronous Read or Write Timing Diagram .................................................6-6
6-5.
Special Asynchronous Read or Write Timing Diagram ....................................6-6
7-1.
DRAM Register (DRAM5–DRAM0) ..................................................................7-1
7-2.
DRAM Timing Mode 1 (Read Cycle, ROM Mode = 0) .....................................7-3
7-3.
DRAM Timing Mode 1 (Read Cycle, ROM Mode = 1) .....................................7-3
7-4.
Address Demultiplexing Example ....................................................................7-4
7-5.
DRAM Control Register ....................................................................................7-5
7-6.
DRAM Refresh Cycle .......................................................................................7-6
7-7.
DRAM Timing Mode 0 (Read Cycle, ROM Mode = 0) .....................................7-7
7-8.
DRAM Timing Mode 1 (Read Cycle, ROM Mode = 0) .....................................7-7
7-9.
DRAM Timing Mode 2 (Read Cycle, ROM Mode = 0) .....................................7-8
7-10.
DRAM Timing Mode 0 (Write Cycle) ................................................................7-8
7-11.
DRAM Timing Mode 1 (Write Cycle) ................................................................7-9
7-12.
DRAM Timing Mode 2 (Write Cycle) ................................................................7-9
8-1.
PDMA and GDMA Configuration Registers .....................................................8-2
8-2.
GDMA Control Register ...................................................................................8-3
8-3.
DMA Speed Register .......................................................................................8-4
8-4.
DMA Interrupt Event Registers ........................................................................8-5
8-5.
GDMA MC68322 Bus Read Or Write Cycle .....................................................8-8
8-6.
Byte-Sized DMA DRAM Write Transfer ...........................................................8-9
8-7.
Word-Sized DMA DRAM Write Transfer ..........................................................8-9
9-1.
Parallel Port Interface Controller Block Diagram ..............................................9-1
9-2.
Parallel Port Interface Register ........................................................................9-2
9-3.
Parallel Port Control Register ...........................................................................9-4
9-4.
PPI Interrupt Event Register ............................................................................9-6
9-5.
Compatibility Mode Timing Diagram ................................................................9-8
9-6.
ECP Mode Timing Diagram .............................................................................9-9
9-7.
Error Cycle Timing Diagram ...........................................................................9-13
9-8.
Parallel Port Data Latch Timing Diagram .......................................................9-13
10-1.
Printer Communication Register ....................................................................10-2
10-2.
PVC Control Register .....................................................................................10-3
10-3.
Printer Control Block Register Set .................................................................10-5
10-4.
PVC Interrupt Event Register .........................................................................10-6
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Freescale Semiconductor, Inc.
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