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| 型號(hào)： | MC68322FT16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.667 MHz, RISC PROCESSOR, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 236/283頁(yè) |
| 文件大?。?/td> | 1602K |
| 代理商： | MC68322FT16 |
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Bus Operation
MOTOROLA
MC68322 USER’S MANUAL
4-9
4.5 EXTERNAL BUS MASTER
The design of the MC68322 bus allows only one bus master at a given time. The core can
be disabled as the bus master so that DMA or an external device can have full access to
MC68322 resources. This provides a significant improvement in performance and takes full
advantage of the high integration in the MC68322. The design also provides the external bus
master with access to DRAM, chip-selects, or register memory resources in the lower 64M
of memory. However, the external bus master cannot access memory above this 64M
boundary. A handshake between the MC68322 and the external bus master achieves the
exchange of bus mastership.
When the MC68322 is in external bus master mode, the external bus master drives many
of the signals into the MC68322. The external bus master is limited in that it is unable to
detect generated interrupts, can perform only word-sized operations, and cannot perform
read-modify-write cycles.
4.5.1 MC68322 Bus Arbitration
Bus arbitration is the protocol by which an external device or DMA becomes the MC68322
bus master. The bus interface unit manages the bus arbitration signals so that the core
alternates cycles between GDMA and the external master. Systems having several devices
that become bus master require external circuitry to assign priorities to the devices. So when
two or more external devices try to become bus master at the same time, the one having the
highest priority is the bus master first. These external devices must assert the bus arbitration
signals in the following sequence:
1. An external device asserts the bus request (BR) signal. This can be a wire-ORed
signal (although it need not be constructed from open-collector devices) that informs
the MC68322 that an external device requires control of the bus.
2. The MC68322 three-states A25–A1, D15–D0, AS, and R/W. Then it asserts the bus
grant (BG) signal to indicate the bus is available.
3. The external device controls the bus cycle by driving the control signals and the
MC68322 asserts EDTACK to denote the end of each external bus master cycle.
BR can be issued at any time during a bus cycle or between cycles. BG is asserted when
the bus is available. When the requesting device receives BG and more than one external
device can be bus master, the requesting device should begin whatever arbitration is
required. The external device asserts and maintains BR during the entire bus cycle (or
cycles) for which it is bus master. The following conditions must be met for an external
device to assume mastership of the bus through the normal bus arbitration procedure:
1. The external device must have received the BG signal through the arbitration process.
2. In a multiple bus master situation, it is important to be sure that only one processor has
the bus at any given time.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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